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C540U C541U
8-Bit CMOS Microcontroller
tp :/ Se /ww mw ic .s on ie du me ct ns or .d / e/
User's Manual 10.97
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C540U/C541U User's Manual Revision History : Previous Releases : Page (previous version) Page (new version)
1997-10-01 Original Version
Subjects (changes since last revision)
Edition 1997-10-01 Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
General Information C541U
Table of Contents 1 1.1 1.2 2 2.1 2.2 3 3.1 3.2 3.3 3.4 4 4.1 4.1.1 4.1.2 4.1.3 4.2 4.3 4.4 4.5 5 5.1 5.2 5.3 5.4 6 6.1 6.1.1 6.1.1.1 6.1.2 6.1.3 6.1.3.1 6.1.3.2 6.1.3.3 6.2 6.2.1 6.2.1.1 6.2.1.2 6.2.1.3 6.2.1.4 6.2.1.5 6.3 6.3.1
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2 CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4 Memory Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 Program Memory, "Code Space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2 Data Memory, "Data Space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 Accessing External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 Role of P0 and P2 as Data/Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3 External Program Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3 PSEN, Program Store Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3 Overlapping External Data and Program Memory Spaces . . . . . . . . . . . . . . . . . . .4-3 ALE, Address Latch Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4 Enhanced Hooks Emulation Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5 Reset and System Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 Hardware Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 Fast Internal Reset after Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3 Hardware Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5 Oscillator and Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6 On-Chip Peripheral Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 Port Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2 Port 0 and Port 2 used as Address/Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-7 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8 Port Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-10 Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-10 Port Loading and Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-11 Read-Modify-Write Feature of Ports 1,2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .6-12 Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-13 Timer/Counter 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-13 Timer/Counter 0 and 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-14 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-17 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-18 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-19 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-20 SSC Interface (C541U only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-21 General Operation of the SSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-22
Semiconductor Group
I-1
General Information C541U
Table of Contents 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.6.1 6.3.6.2 6.3.7 6.4 6.4.1 6.4.2 6.4.2.1 6.4.2.2 6.4.2.2.1 6.4.2.2.2 6.4.2.3 6.4.3 6.4.4 6.4.5 6.4.6 6.4.6.1 6.4.6.2 6.4.6.3 6.4.7 6.4.7.1 6.4.7.2 6.4.7.3 6.4.8 6.4.9 6.4.10 6.4.10.1 6.4.10.2 7 7.1 7.1.1 7.1.2 7.1.3 7.2 7.3 7.4 7.5 8 8.1 8.1.1
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Enable/Disable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-22 Baudrate Generation (Master Mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-23 Write Collision Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-23 Master/Slave Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-24 Data/Clock Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-25 Master Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-25 Slave Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-26 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-27 USB Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-32 Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-33 USB Memory Buffer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-34 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-34 Single Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-35 USB Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-35 USB Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-37 Dual Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-40 USB Memory Buffer Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-47 USB Memory Buffer Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-48 Initialization of USB Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-49 Control Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-51 Setup Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-51 Data Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-51 Status Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-51 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-52 Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-53 Device Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-57 Endpoint Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-64 On-Chip USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-73 Detection of Connected Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-75 Detach / Attach Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-76 Self-Powered Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-76 Bus-Powered Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-76 Interrupt System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4 Interrupt Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4 Interrupt Request / Control Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-9 Interrupt Prioritiy Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-14 Interrupt Priority Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-15 How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-16 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-18 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-20 Fail Safe Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1 Programmable Watchdog Timer (C541U only) . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1 Input Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2
Semiconductor Group
I-2
General Information C541U
Table of Contents 8.1.2 8.1.3 8.1.4 8.1.5 8.2 8.2.1 8.2.2 9 9.1 9.1.1 9.1.2 9.2 9.2.1 9.2.2 9.2.2.1 9.2.2.2 10 10.1 10.2 10.3 10.4 10.4.1 10.4.2 10.5 10.6 10.7 10.8 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 12
Page
Watchdog Timer Control / Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3 Starting the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4 Refreshing the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4 Watchdog Reset and Watchdog Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4 Oscillator Watchdog Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-5 Functionality of the Oscillator Watchdog Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-6 Fast Internal Reset after Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-7 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3 Entering Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4 Exit from Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-5 Entering Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-6 Exit from Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7 Exit via Pin P3.2/INT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8 Exit via UBS Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8 OTP Memory Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1 Programming Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-2 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-4 Programming Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-6 Basic Programming Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-6 OTP Memory Access Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-7 Program / Read OTP Memory Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-8 Lock Bits Programming / Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-10 Access of Version Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-12 OTP Verify with Protection Level 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-13 Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-2 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-4 AC Characteristics of Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-12 OTP Verification Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-16 USB Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-17 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-20 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1
Semiconductor Group
I-3
Introduction C540U / C541U
1
Introduction
The C540U and C541U are members of the Siemens C500 family of 8-bit microcontrollers They are fully compatible to the standard 80C51 architecture. The C540U/C541U especially provide an on-chip USB module compliant to the USB specification, which is capable to operate either in low or full speed mode. The five endpoints can be easily controlled by the CPU via special function registers. Due to the on-chip USB transceiver circuits the C540U/C541U can be directly connected to the USB bus. Figure 1-1 shows the different functional units of the C540U/C541U and figure 1-2 shows the simplified logic symbol of the C540U/C541U.
On-Chip Emulation Support Module
Oscillator Watchdog
Watchdog Timer SSC T0
RAM 256 x 8
Port 0
I/O
Port 1 CPU
I/O
Power Saving Modes
USB Module USB Transceiver D+ D-
T1 OTP Prog. Memory C540U : 4 k x 8 C541U : 8 k x 8
Port 2
I/O
Port 3
I/O
The shaded units are not available in the C540U.
MCA03373
Figure 1-1 C540U/C541U Functional Units
Semiconductor Group
1-1
1997-10-01
Introduction C540U / C541U
Listed below is a summary of the main features of the C541U :
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*
* * * * * * *
Enhanced 8-bit C500 CPU - Full software/toolset compatible to standard 80C51/80C52 microcontrollers 12 MHz external operating frequency - 500 ns instruction cycle Built-in PLL for USB synchronization On-chip OTP program memory - C540U : 4K byte - C541U : 8K byte - Alternatively up to 64K byte external program memory - Optional memory protection Up to 64K byte external data memory 256 byte on-chip RAM Four parallel I/O ports - P-LCC-44 package : three 8-bit ports and one 6-bit port - P-SDIP-52 package : four 8-bit ports - LED current drive capability for 3 pins (10 mA) Two 16-bit timer/counters (C501 compatible) On-chip USB module - Compliant to USB specification - Full speed or low speed operation - Five endpoints : one bidirectional control endpoint four versatile programmable endpoints - Registers are located in special function register area - On-chip USB transceiver SSC synchronous serial interface (SPI compatible) (only C541U) - Master and slave capable - Programmable clock polarity / clock-edge to data phase relation - LSB/MSB first selectable - 1.5 MBaud transfer rate at 12 MHz operating frequency 7 interrupt sources (2 external, 5 internal with 2 USB interrupts) selectable at 2 priority levels Enhanced fail safe mechanisms - Programmable watchdog timer (only C541U) - Oscillator watchdog Power saving modes - idle mode - software power down mode with wake-up capability through INT0 pin or USB On-chip emulation support logic (Enhanced Hooks Technology TM) P-LCC-44 and P-SDIP-52 packages Power supply voltage range : 4.0V to 5.5V Temperature Range : SAB-C540U TA = 0 to 70 C SAB-C541U TA = 0 to 70 C
Semiconductor Group
1-2
1997-10-01
Introduction C540U / C541U
V CC
V SS
XTAL2 XTAL1 ALE PSEN EA RESET D+ DC540U C541U
Port 0 8-Bit Digital I / O Port 1 P-LCC-44 : 6-Bit Digital I / O P-SDIP-52 : 8-Bit Digital I / O Port 2 8-Bit Digital I / O Port 3 8-Bit Digital I / O
MCL03374
Figure 1-2 Logic Symbol
Semiconductor Group
1-3
1997-10-01
Introduction C540U / C541U
1.1
Pin Configuration
This section describes the pin configrations of the C540U/C541U in the P-LCC-44 and P-SDIP-52 packages.
P1.1 / LED1 P1.0 / LED0 DD+ V SSU V CCU P1.5 / SLS P0.0 / AD0 P0.1 / AD1 P0.2 / AD2 P0.3 / AD3 6 5 4 3 2 1 44 43 42 41 40 P1.2 / SCLK V CC V SS RESET P3.0 / LED2 P1.3 / SRI P3.1 / DADD P3.2 / INT0 P3.3 / INT1 P3.4 / T0 P3.5 / T1 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 P0.4 / AD4 P0.5 / AD5 P0.6 / AD6 P0.7 / AD7 EA P1.4 / STO ALE PSEN P2.7 / A15 P2.6 / A14 P2.5 / A13
C540U C541U
18 19 20 21 22 23 24 25 26 27 28 P3.6 / WR P3.7 / RD XTAL2 XTAL1 V SS V CC P2.0 / A8 P2.1 / A9 P2.2 / A10 P2.3 / A11 P2.4 / A12 This pin functionality ist not available for the C540U.
MCP03343
Figure 1-3 Pin Configuration P-LCC-44 Package (top view)
Semiconductor Group
1-4
1997-10-01
Introduction C540U / C541U
V CCU V SSU
D+ DN.C. N.C. P1.0 / LED0 P1.1 / LED1 P1.2 / SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
N.C. P1.5 / SLS P0.0 / AD0 P0.1 / AD1 P0.2 / AD2 P0.3 / AD3 P0.4 / AD4 P0.5 / AD5 P0.6 / AD6 P0.7 / AD7 EA P1.4 / STO P1.7 ALE PSEN N.C. N.C. P2.7 / A15 P2.6 / A14 P2.5 / A13 P2.4 / A12 P2.3 / A11 P2.2 / A10 P2.1 / A9 P2.0 / A8 N.C.
MCP03344
V CC V SS
RESET P3.0 / LED2 P1.3 / SRI P1.6 P3.1 / DADD P3.2 / INT0 P3.3 / INT1 P3.4 / T0 P3.5 / T1 P3.6 / WR P3.7 / RD XTAL2 XTAL1
C540U C541U
V SS V CC
This pin functionality ist not available for the C540U.
Figure 1-4 Pin Configuration P-SDIP-52 Package (top view)
Semiconductor Group
1-5
1997-10-01
Introduction C540U / C541U
1.2
Pin Definitions and Functions
This section describes all external signals of the C541U with its function. Table 1-1 Pin Definitions and Functions Symbol D+ 3 Pin Numbers P-LCC-44 P-SDIP-52 3 I/O USB D+ Data Line The pin D+ can be directly connected to USB cable (transceiver is integrated on-chip). USB D- Data Line The pin D- can be directly connected to USB cable (transceiver is integrated on-chip). Port 1 is an 6-bit (P-LCC-44) or 8-bit (P-SDIP-52) quasibidirectional I/O port with internal pullup resistors. Port 1 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 1 also contains two outputs with LED drive capability as well as the four pins of the SSC (C541U only). The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except when used for the compare functions). The secondary functions are assigned to the port 1 pins as follows : P1.0 / LED0 LED0 output P1.1 / LED1 LED1 output P1.2 / SCLK SSC Master Clock Output / SSC Slave Clock Input (C541U only) P1.3 / SRI SSC Receive Input (C541U only) P1.4 / STO SSC Transmit Output (C541U only) P1.5 / SLS SSC Slave Select Inp. (C541U only) P1.6 (P-SDIP-52 only) P1.7 (P-SDIP-52 only) I/O*) Function
D-
4
4
I/O
P1.0 - P1.4
5 - 7, 7 - 9, 14, 41, I/O 12, 34, 44 51, 15, 40
5 6 7 12 34 44 - -
*) I = Input O = Output
7 8 9 13 41 51 15 40
Semiconductor Group
1-6
1997-10-01
Introduction C540U / C541U
Table 1-1 Pin Definitions and Functions Symbol RESET 10 Pin Numbers P-LCC-44
(cont'd) I/O*) Function I RESET A high level on this pin for the duration of two machine cycles while the oscillator is running resets the C540U/C541U. A small internal pulldown resistor permits power-on reset using only a capacitor connected to VCC . Port 3 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 3 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 3 also contains the interrupt, timer, serial port and external memory strobe pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: P3.0 / LED2 LED2 output P3.1 / DADD Device attached input P3.2 / INT0 External interrupt 0 input / timer 0 gate control input External interrupt 1 input / P3.3 / INT1 timer 1 gate control input P3.4 / T0 Timer 0 counter input P3.5 / T1 Timer 1 counter input P3.6 / WR WR control output; latches the data byte from port 0 into the external data memory P3.7 / RD RD control output; enables the external data memory XTAL2 is the output of the inverting oscillator amplifier. This pin is used for the oscillator operation with crystal or ceramic resonator.
P-SDIP-52 12
P3.0 - P3.7
11, 13 - 19 13, 16 - 22
I/O
XTAL2
20
23
-
*) I = Input O = Output
Semiconductor Group
1-7
1997-10-01
Introduction C540U / C541U
Table 1-1 Pin Definitions and Functions Symbol XTAL1 21 Pin Numbers P-LCC-44
(cont'd) I/O*) Function - XTAL1 is the input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed. Port 2 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing 1's. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register. The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods except during external data memory accesses. The signal remains high during internal program execution. The Address Latch enable output is used for latching the address into external memory during normal operation. It is activated every six oscillator periods except during an external data memory access.
P-SDIP-52 24
P2.0 - P2.7
24 - 31
28 - 35
I/O
PSEN
32
38
O
ALE
33
39
O
*) I = Input O = Output
Semiconductor Group
1-8
1997-10-01
Introduction C540U / C541U
Table 1-1 Pin Definitions and Functions Symbol EA 35 Pin Numbers P-LCC-44
(cont'd) I/O*) Function I External Access Enable When held high, the C540U/C541U executes instructions from the internal ROM as long as the PC is less than 1000H for the C540U or less than 2000H for the C541U. When held low, the C540U/ C541U fetches all instructions from external program memory. For the C540U-L/C541U-L this pin must be tied low. Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pullup resistors when issuing 1's. Supply voltage for the on-chip USB transceiver circuitry. Ground (0V) for the on-chip USB transceiver circuitry. Supply voltage for ports and internal logic circuitry during normal, idle, and power down mode. Ground (0V) for ports and internal logic circuitry during normal, idle, and power down mode.
P-SDIP-52 42
P0.0 - P0.7
44 - 36
50 - 43
I/O
VCCU VSSU VCC
1 2 8, 23
1 2 10, 26
- - -
VSS
9, 22
11, 25
-
*) I = Input O = Output
Semiconductor Group
1-9
1997-10-01
Introduction C540U / C541U
Semiconductor Group
1-10
1997-10-01
Fundamental Structure C540U / C541U
2
Fundamental Structure
The C540U/C541U is fully compatible to the architecture of the standard 8051/C501 microcontroller family. While maintaining the typical architectural characteristics of the C501, the C541U incorporates a SSC synchronous serial interface, a versatile USB module as well as some enhancements in the Fail Save Mechanism Unit. Functionally, the C540U is a subset of the C541U with a smaller OTP program memory and without the SSC interface and the watchdog timer. Figure 2-1 shows a block diagram of the C540U/C541U.
Oscillator Watchdog XTAL2 XTAL1 ALE PSEN EA RESET Progr. Watchdog Timer (C541U only) Timer 0 Timer 1 CPU OSC & Timing
RAM 256 x 8
OTP Memory 4k x 8 (C540U) 8k x 8 (C541U)
Emulation Support Logic Port 0 Port 0 8-Bit Digit. I/O Port 1 1) 6- / 8-Bit Digit. I/O Port 2 8-Bit Digit. I/O Port 3 8-Bit Digit. I/O
Port 1 SSC (SPI) Interface (C541U only) Transceiver PLL USB Module Port 2
D+ D-
Port 3
Interrupt Unit
1)
C540U C541U
MCB03345
P-LCC-44 : 6-Bit Port; P-SDIP-52 : 8-Bit Port
Figure 2-1 Block Diagram of the C540U/C541U
Semiconductor Group
2-1
1997-10-01
Fundamental Structure C540U / C541U
2.1
CPU
The CPU is designed to operate on bits and bytes. The instructions, which consist of up to 3 bytes, are performed in one, two or four machine cycles. One machine cycle requires six oscillator cycles (this number of oscillator cycles differs from other members of the C500 microcontroller family). The instruction set has extensive facilities for data transfer, logic and arithmetic instructions. The Boolean processor has its own full-featured and bit-based instructions within the instruction set. The C541U uses five addressing modes: direct access, immediate, register, register indirect access, and for accessing the external data or program memory portions a base register plus index-register indirect addressing. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12 MHz clock, 58% of the instructions execute in 500 ns. The CPU (Central Processing Unit) of the C540U/C541U consists of the instruction decoder, the arithmetic section and the program control section. Each program instruction is decoded by the instruction decoder. This unit generates the internal signals controlling the functions of the individual units within the CPU. They have an effect on the source and destination of data transfers and control the ALU processing. The arithmetic section of the processor performs extensive data manipulation and is comprised of the arithmetic/logic unit (ALU), an A register, B register and PSW register. The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the instruction decoder. The ALU performs the arithmetic operations add, substract, multiply, divide, increment, decrement, BDC-decimal-add-adjust and compare, and the logic operations AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble (left four)). Also included is a Boolean processor performing the bit operations as set, clear, complement, jumpif-not-set, jump-if-set-and-clear and move to/from carry. Between any addressable bit (or its complement) and the carry flag, it can perform the bit operations of logical AND or logical OR with the result returned to the carry flag. The program control section controls the sequence in which the instructions stored in program memory are executed. The 16-bit program counter (PC) holds the address of the next instruction to be executed. The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence.
Accumulator ACC is the symbol for the accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as A.
Program Status Word The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU.
Semiconductor Group
2-2
1997-10-01
Fundamental Structure C540U / C541U
Special Function Register PSW (Address D0H) Bit No. MSB D7H D0H CY D6H AC D5H F0 D4H RS1 D3H RS0 D2H OV D1H F1
Reset Value : 00H LSB D0H P PSW
Bit CY AC F0 RS1 RS0
Function Carry Flag Used by arithmetic instruction. Auxiliary Carry Flag Used by instructions which execute BCD operations. General Purpose Flag Register Bank select control bits These bits are used to select one of the four register banks. RS1 0 0 1 1 RS0 0 1 0 1 Function Bank 0 selected, data address 00H-07H Bank 1 selected, data address 08H-0FH Bank 2 selected, data address 10H-17H Bank 3 selected, data address 18H-1FH
OV F1 P
Overflow Flag Used by arithmetic instruction. General Purpose Flag Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity.
B Register The B register is used during multiply and divide and serves as both source and destination. For other instructions it can be treated as another scratch pad register. Stack Pointer The stack pointer (SP) register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET (RETI) execution, i.e. it always points to the last valid stack byte. While the stack may reside anywhere in the on-chip RAM, the stack pointer is initialized to 07H after a reset. This causes the stack to begin a location = 08H above register bank zero. The SP can be read or written under software control.
Semiconductor Group
2-3
1997-10-01
Fundamental Structure C540U / C541U
2.2
CPU Timing
The C540U/C541U has no clock prescaler. Therefore, a machine cycle of the C540U/C541U consists of 6 states (6 oscillator periods). Each state is devided into a phase 1 half and a phase 2 half. Thus, a machine cycle consists of 6 oscillator periods, numbererd S1P1 (state 1, phase 1) through S6P2 (state 6, phase 2). Each state lasts one oscillator period. Typically, arithmetic and logic operations take place during phase 1 and internal register-to-register transfers take place during phase 2. The diagrams in figure 2-2 show the fetch/execute timing related to the internal states and phases. Since these internal clock signals are not user-accessible, the XTAL2 oscillator signals and the ALE (address latch enable) signal are shown for external reference. ALE is normally activated twice during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1. Executing of a one-cycle instruction begins at S1P2, when the op-code is latched into the instruction register. If it is a two-byte instruction, the second reading takes place during S4 of the same machine cycle. If it is a one-byte instruction, there is still a fetch at S4, but the byte read (which would be the next op-code) is ignored (discarded fetch), and the program counter is not incremented. In any case, execution is completed at the end of S6P2. Figures 2-2 (a) and (b) show the timing of a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle instruction.
Semiconductor Group
2-4
1997-10-01
Fundamental Structure C540U / C541U
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 OSC (XTAL2) ALE Read Opcode S1 S2 S3 S4 Read Next Opcode (Discard) S5 S6 Read Next Opcode Again
(a) 1-Byte, 1-Cycle Instruction, e. g. INC A Read Opcode S1 S2 S3 S4 Read 2nd Byte S5 S6 Read Next Opcode
(b) 2-Byte, 1-Cycle Instruction, e. g. ADD A #DATA Read Opcode S1 S2 S3 S4 Read Next Opcode (Discard) Read Next Opcode Again S4 S5 S6
S5
S6
S1
S2
S3
(c) 1-Byte, 2-Cycle Instruction, e. g. INC DPTR Read Opcode (MOVX) S1 S2 S3 S4 Read Next Opcode (Discard) S5 ADDR S6 S1 Read Next Opcode Again No Fetch No Fetch No ALE S2 DATA
MCD03287
S3
S4
S5
S6
(d) MOVX (1-Byte, 2-Cycle)
Access of External Memory
Figure 2-2 Fetch Execute Sequence
Semiconductor Group
2-5
1997-10-01
Fundamental Structure C540U / C541U
Semiconductor Group
2-6
1997-10-01
Memory Organization C540U / C541U
3
Memory Organization
The C540U/C541U CPU manipulates operands in the following four address spaces: - - - - - 8 or 4 KByte on-chip OTP program memory Totally up to 64 Kbyte internal/external program memory up to 64 Kbyte of external data memory 256 bytes of internal data memory a 128 byte special function register area
Figure 3-3 illustrates the memory address spaces of the C540U/C541U.
FFFF H
FFFF H
External External Indirect Addr. Internal RAM 2000 H 1) 1FFF H 1) Internal (EA = 1) External (EA = 0) 0000 H "Code Space" 0000 H "External Data Space" Internal RAM 00 H "Internal Data Space"
MCD03375
FF H
Direct Addr. Special Function Register
FF H
80 H 7F H
80 H
1) For the C504U the int. / ext. program memory boundary is at 0FFF H / 1000 H .
Figure 3-3 C540U/C541U Memory Map
Semiconductor Group
3-1
1997-10-01
Memory Organization C540U / C541U
3.1
Program Memory, "Code Space"
The C541U has 8 Kbyte (C540U : 4 Kbyte) of OTP program memory which can be externally expanded up to 64 Kbytes. If the EA pin is held high, the C541U executes program code out of the internal OTP program memory unless the program counter address exceeds 1FFFH (C540U : 0FFFH). Address locations 2000H through FFFFH (C540U : 1000H through 0FFFH) are then fetched from the external program memory. If the EA pin is held low, the C540U/C541U fetches all instructions from the external 64K byte program memory. 3.2 Data Memory, "Data Space"
The data memory address space consists of an internal and an external memory space. The internal data memory is divided into three physically separate and distinct blocks : the lower 128 bytes of RAM, the upper 128 bytes of RAM, and the 128 byte special function register (SFR) area. While the upper 128 bytes of data memory and the SFR area share the same address locations, they are accessed through different addressing modes. The lower 128 bytes of data memory can be accessed through direct or register indirect addressing; the upper 128 bytes of RAM can be accessed through register indirect addressing; the special function registers are accessible through direct addressing. Four 8-register banks, each bank consisting of eight 8-bit multi-purpose registers, occupy locations 0 through 1FH in the lower RAM area. The next 16 bytes, locations 20H through 2FH, contain 128 directly addressable bit locations. The stack can be located anywhere in the internal data memory address space, and the stack depth can be expanded up to 256 bytes. The external data memory can be expanded up to 64 Kbyte and can be accessed by MOVX instructions that use a 16-bit or an 8-bit address. Note :The registers of the USB module are accessed through special function registers in the SFR area. 3.3 General Purpose Registers
The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the PSW in chapter 2). This allows fast context switching, which is useful when entering subroutines or interrupt service routines. The 8 general purpose registers of the selected register bank may be accessed by register addressing. With register addressing the instruction op code indicates which register is to be used. For indirect addressing R0 and R1 are used as pointer or index register to address internal or external memory (e.g. MOV @R0). Reset initializes the stack pointer to location 07H and increments it once to start from location 08H which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one register bank, the SP should be initialized to a different location of the RAM which is not used for data storage.
Semiconductor Group
3-2
1997-10-01
Memory Organization C540U / C541U
3.4
Special Function Registers
The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions: the standard special function register area and the mapped special function register area. One special function register of the C540U/C541U (PCON1) is located in the mapped special function register area. All other SFRs are located in the standard special function register area. For accessing PCON1 in the mapped special function register area, bit RMAP in special function register SYSCON must be set. Special Function Register SYSCON (Address B1H) Bit No. MSB 7 B1H - Reset Value : XX10XXXXB LSB 0 - SYSCON
6 -
5 EALE
4 RMAP
3 -
2 -
1 -
The functions of the shaded bits are not described in this section.
Bit RMAP
Function Special function register map bit RMAP = 0 : The access to the non-mapped (standard) special function register area is enabled. RMAP = 1 : The access to the mapped special function register area (PCON1) is enabled.
As long as bit RMAP is set, a mapped special function register can be accessed. This bit is not cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must be cleared/set by software, respectively each. The registers, except the program counter and the four general purpose register banks, reside in the special function register area. All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are bitaddressable. The 75 special function registers (SFRs) in the SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C540U/C541U are listed in table 3-2 and table 3-3. In table 3-2 they are organized in groups which refer to the functional blocks of the C540U/C541U. Table 3-3 illustrates the contents of the SFRs in numeric order of their addresses.
Semiconductor Group
3-3
1997-10-01
Memory Organization C540U / C541U
Table 3-2 Special Function Registers - Functional Blocks Block CPU Symbol ACC B DPH DPL PSW SP VR0 VR1 VR2 SYSCON IEN0 IEN1 IP0 IP1 ITCON P0 P1 P2 P3 TCON TH0 TH1 TL0 TL1 TMOD SSCCON STB SRB SCF SCIEN SSCMOD Name Accumulator B Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer Version Register 0 Version Register 1 Version Register 2 System Control Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Interrupt Priority Register 1 External Interrupt Trigger Condition Register Port 0 Port 1 Port 2 Port 3 Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register SSC Control Register SSC Transmit Buffer SSC Receive Register SSC Flag Register SSC Interrupt Enable Register SSC Mode Test Register Watchdog Timer Control Register Watchdog Timer Reload Register Address Contents after Reset E0H 1) F0H 1) 83H 82H D0H 1) 81H FCH FDH FEH B1H A8H1) A9H B8H 1) B9H) 9AH 80H 1) 90H 1) A0H 1) B0H 1) 88H 1) 8CH 8DH 8AH 8BH 89H 93H 1) 94H 95H ABH 1) ACH 96H C0H 1) 86H 00H 00H 00H 00H 00H 07H C5H C1H YYH 3) XX10XXXXB 2) 0XXX0000B 2) XXXXX000B 2) XXXX0000B 2) XXXXX000B 2) XXXX1010B 2) FFH FFH FFH FFH 00H 00H 00H 00H 00H 00H 07H XXH 2) XXH 2) XXXXXX00B 2) XXXXXX00B 2) 00H XXXX0000B 2) 00H
Interrupt System
Ports
Timer 0 / Timer 1
SSC Interface (C541U only)
Watchdog WDCON (C541U WDTREL only)
1) Bit-addressable special function registers 2) "X" means that the value is undefined and the location is reserved 3) The content of this SFR varies with the actual of the step C540U/C541U (eg. 01H for the first step) 4) This SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
Semiconductor Group
3-4
1997-10-01
Memory Organization C540U / C541U
Table 3-2 Special Function Registers - Functional Blocks (cont'd) Block Pow. Sav. Modes USB Module Symbol PCON PCON1 EPSEL USBVAL ADROFF GEPIR DCR DPWDR DIER DIRR FNRL FNRH EPBCn 1) EPBSn 1) EPIEn 1) EPIRn 1) EPBAn 1) EPLENn 1) Name Power Control Register Power Control Register 1 USB Endpoint Select Register USB Data Register USB Address Offset Register USB Global Endpoint Interrupt Request Reg. USB Device Control Register USB Device Power Down Register USB Device Interrupt Control Register USB Device Interrupt Request Register USB Frame Number Register, Low Byte USB Frame Number Register, High Byte USB Endpoint n Buffer Control Register USB Endpoint n Buffer Status Register USB Endpoint n Interrupt Enable Register USB Endpoint n Interrupt Request Register USB Endpoint n Base Address Register USB Endpoint n Buffer Length Register Address Contents after Reset 87H 88H 4) D2H D3H D4H D6H C1H C2H C3H C4H C6H C7H C1H C2H C3H C4H C5H C6H X00X0000B 2) 0XX0XXXXB 2) 80H 00H 00H 2) 00H 000X0000B 00H 00H 00H XXH 00000XXXB 00H 20H 00H 10H 3) 00H 0XXXXXXXB
1) These register are multiple registers (n=0-4) with the same SFR address; selection of register "n" is done by SFR EPSEL. 2) The reset value of ADROFF is valid only if USBVAL has not been read or written since the last hardware reset. 3) The reset value of EPIR0 is 11H.
Semiconductor Group
3-5
1997-10-01
Memory Organization C540U / C541U
Table 3-3 Contents of the SFRs, SFRs in numeric order of their addresses Addr Register Reset Bit 7 Value1) 80H 2) P0 81H 82H 83H 86H 4) 87H SP DPL DPH FFH 07H 00H .7 .7 .7 .7 WDT PSEL - TF1 Bit 6 .6 .6 .6 .6 .6 PDS TR1 Bit 5 .5 .5 .5 .5 .5 IDLS TF0 - M1 .5 .5 .5 .5 SLS MSTR .5 .5 0 - .5 - - - Bit 4 .4 .4 .4 .4 .4 - TR0 WS M0 .4 .4 .4 .4 STO CPOL .4 .4 0 - .4 - - - Bit 3 .3 .3 .3 .3 .3 GF1 IE1 - GATE .3 .3 .3 .3 SRI CPHA .3 .3 0 I1ETF .3 ET1 - - Bit 2 .2 .2 .2 .2 .2 GF0 IT1 - C/T .2 .2 .2 .2 SCLK BRS2 .2 .2 0 I1ETR .2 EX1 EUDI - Bit 1 .1 .1 .1 .1 .1 PDE IE0 - M1 .1 .1 .1 .1 LED1 BRS1 .1 .1 0 I0ETF .1 ET0 EUEI Bit 0 .0 .0 .0 .0 .0 IDLE IT0 - M0 .0 .0 .0 .0 LED0 BRS0 .0 .0 LSBSM I0ETR .0 EX0 ESSC
00H WDTREL 00H X00X0000B 00H 0XX0XXXXB 00H 00H 00H 00H 00H FFH
PCON
88H 2) TCON 88H
2) 3)
PCON1 TMOD TL0 TL1 TH0 TH1
EWPD - GATE .7 .7 .7 .7 .7 SCEN .7 .7 - .7 EA - - C/T .6 .6 .6 .6 .6 TEN .6 .6 - .6 - - -
89H 8AH 8BH 8CH 8DH
90H2) P1
93H 4) SSCCON 07H XXH 94H 4) STB 95H 9AH
4)
SRB
96H 4)
XXH SSCMOD 00H ITCON XXXX1010B FFH 0XXX0000B XXXXX000B XXXXXX00B
LOOPB TRIO
A0H2) P2 A8H2) IEN0 A9H IEN1
ABH SCF
4)
WCOL TC
1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) This SFR is only available in the C541U.
Semiconductor Group
3-6
1997-10-01
Memory Organization C540U / C541U
Table 3-3 Contents of the SFRs, SFRs in numeric order of their addresses (cont'd) Addr Register Reset Bit 7 Value1) ACH SCIEN
4)
Bit 6 - WR - - - -
Bit 5 - T1 EALE - - -
Bit 4 - T0 RMAP - - -
Bit 3 - INT1 - PT1 -
Bit 2 - INT0 - PX1 PUDI
Bit 1
Bit 0
XXXXXX00B FFH
- RD - - - -
WCEN TCEN DADD - PT0 PUEI LED2 - PX0 PSSC
4)
B0H2) P3 B1H
SYSCON XX10XXXXB XXXX0000B XXXX0000B XXXX0000B 00H
B8H2) IP0 B9H C0H
2)
IP1
WDCON
OWDS WDTS WDT
SWDT
C1H to C7H D0H
2)
USB Device and Endpoint Register definition see table 3-3 CY EPS7 .7
7)
PSW EPSEL
AC 0 .6 0 0 .6 .6 1 1 .6
F0 0 .5 AO5 0 .5 .5 0 0 .5
RS1 0 .4 AO4 EPI4 .4 .4 0 0 .4
RS0 0 .3 AO3 EPI3 .3 .3 0 0 .3
OV EPS2 .2 AO2 EPI2 .2 .2 1 0 .2
F1 EPS1 .1 AO1 EPI1 .1 .1 0 0 .1
P EPS0 .0 AO0 EPI0 .0 .0 1 1 .0
D2H D3H D4H
80H USBVAL 00H
ADROFF 00H D6H GEPIR 00H E0H2) ACC 00H F0H2) B 00H C5H C1H
6)
0 0 .7 .7 1 1 .7
FCH VR0
3) 5)
FDH VR1
3) 5)
FEH
3) 5)
VR2
1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) This SFR respectively bit is only available in the C541U. 5) These are read-only registers 6) The content of this SFR varies with the actual of the step C541U (e.g. 01H for the first step) 7) The reset value of ADROFF is valid only if USBVAL has not been read or written since the last hardware reset.
Semiconductor Group
3-7
1997-10-01
Memory Organization C540U / C541U
Table 3-4 Contents of the USB Device and Endpoint Registers (Addr. C1H to C7H) Addr Register Reset Value C1H DCR 000X. 0000B Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
EPSEL = 1XXX.XXXXB Device Registers
SPEED 0 SE0IE SE0I DA 0 DAIE DAI SWR 0 DDIE DDI SUSP 0 SBIE SBI DINIT 0 SEIE SEI RSM 0 STIE STI UCLK TPWD SUIE SUI PCLK RPWD SOFIE SOFI
C2H DPWDR 00H C3H DIER 00H C4H DIRR C5H reserved C6H FNRL C7H FNRH 00H
FNR7 XXH 0 0000. 0XXXB
FNR6 0
FNR5 0
FNR4 0
FNR3 0
FNR2 FNR10
FNR1 FNR9
FNR0 FNR8
EPSEL = 0XXX.X000B C1H EPBC0 C2H EPBS0 C3H EPIE0 C4H EPIR0 C5H EPBA0 00H 20H 00H 11H
Endpoint 0 Registers
STALL0 0 UBF0 AIE0 ACK0 CBF0 NAIE0 NACK0 0 L06 0 DIR0 RLEIE0 RLE0 0 L05 GEPIE0 ESP0 SOFDE0 INCE0 0 DBM0 SETRD0 SETWR0 CLREP0 DONE0 DNRIE0 NODIE0 EODIE0 SODIE0 DNR0 A06 L03 NOD0 A05 L02 EOD0 A04 L01 SOD0 A03 L00
- -
0 L04
PAGE0 00H C6H EPLEN0 0XXX. 0 XXXXB
C7H reserved EPSEL = 0XXX.X001B C1H EPBC1 C2H EPBS1 C3H EPIE1 C4H EPIR1 C5H EPBA1 00H 20H 00H 10H Endpoint 1 Registers
STALL1 0 UBF1 AIE1 ACK1 CBF1 NAIE1 NACK1 0 L16 0 DIR1 RLEIE1 RLE1 0 L15 GEPIE1 ESP1 SOFDE1 INCE1 0 DBM1 SETRD1 SETWR1 CLREP1 DONE1 DNRIE1 NODIE1 EODIE1 SODIE1 DNR1 A16 L13 NOD1 A15 L12 EOD1 A14 L11 SOD1 A13 L10
- -
0 L14
PAGE1 00H C6H EPLEN1 0XXX. 0 XXXXB
C7H reserved
Semiconductor Group
3-8
1997-10-01
Memory Organization C540U / C541U
Table 3-4 Contents of the USB Device and Endpoint Registers (Addr. C1H to C7H) (cont'd) Addr Register Reset Value EPSEL = 0XXX.X010B C1H EPBC2 C2H EPBS2 C3H EPIE2 C4H EPIR2 C5H EPBA2 00H 20H 00H 10H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Endpoint 2 Registers
STALL2 0 UBF2 AIE2 ACK2 CBF2 NAIE2 NACK2 0 L62 0 DIR2 RLEIE2 RLE2 0 L52 GEPIE2 ESP2 SOFDE2 INCE2 0 DBM2 SETRD2 SETWR2 CLREP2 DONE2 DNRIE2 NODIE2 EODIE2 SODIE2 DNR2 A62 L32 NOD2 A52 L22 EOD2 A42 L12 SOD2 A32 L02
- -
0 L42
PAGE2 00H C6H EPLEN2 0XXX. 0 XXXXB
C7H reserved EPSEL = 0XXX.X011B C1H EPBC3 C2H EPBS3 C3H EPIE3 C4H EPIR3 C5H EPBA3 00H 20H 00H 10H Endpoint 3 Registers
STALL3 0 UBF3 AIE3 ACK3 CBF3 NAIE3 NACK3 0 L63 0 DIR3 RLEIE3 RLE3 0 L53 GEPIE3 ESP3 SOFDE3 INCE3 0 DBM3 SETRD3 SETWR3 CLREP3 DONE3 DNRIE3 NODIE3 EODIE3 SODIE3 DNR3 A63 L33 NOD3 A52 L23 EOD3 A43 L13 SOD3 A33 L03
- -
0 L43
PAGE3 00H C6H EPLEN3 0XXX. 0 XXXXB
C7H reserved EPSEL = 0XXX.X100B C1H EPBC4 C2H EPBS4 C3H EPIE4 C4H EPIR4 C5H EPBA4 00H 20H 00H 10H Endpoint 4 Registers
STALL4 0 UBF4 AIE4 ACK4 CBF4 NAIE4 NACK4 0 L64 0 DIR4 RLEIE4 RLE4 0 L54 GEPIE4 ESP4 SOFDE4 INCE4 0 DBM4 SETRD4 SETWR4 CLREP4 DONE4 DNRIE4 NODIE4 EODIE4 SODIE4 DNR4 A64 L34 NOD4 A54 L24 EOD4 A44 L14 SOD4 A34 L04
- -4
0 L44
PAGE4 00H C6H EPLEN4 0XXX. 0 XXXXB
C7H reserved
Semiconductor Group
3-9
1997-10-01
Memory Organization C540U / C541U
Semiconductor Group
3-10
1997-10-01
External Bus Interface C540U / C541U
4
External Bus Interface
The C540U/C541U allows for external memory expansion. The functionality and implementation of the external bus interface is identical to the common interface for the 8051 architecture. 4.1 Accessing External Memory
It is possible to distinguish between accesses to external program memory and external data memory or other peripheral components respectively. This distinction is made by hardware: accesses to external program memory use the signal PSEN (program store enable) as a read strobe. Accesses to external data memory use RD and WR to strobe the memory (alternate functions of P3.7 and P3.6). Port 0 and port 2 (with exceptions) are used to provide data and address signals. In this section only the port 0 and port 2 functions relevant to external memory accesses are described. Fetches from external program memory always use a 16-bit address. Accesses to external data memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit address (MOVX @Ri). 4.1.1 Role of P0 and P2 as Data/Address Bus When used for accessing external memory, port 0 provides the data byte time-multiplexed with the low byte of the address. In this state, port 0 is disconnected from its own port latch, and the address/ data signal drives both FETs in the port 0 output buffers. Thus, in this application, the port 0 pins are not open-drain outputs and do not require external pullup resistors. During any access to external memory, the CPU writes FFH to the port 0 latch (the special function register), thus obliterating whatever information the port 0 SFR may have been holding. Whenever a 16-bit address is used, the high byte of the address comes out on port 2, where it is held for the duration of the read or write cycle. During this time, the port 2 lines are disconnected from the port 2 latch (the special function register). Thus the port 2 latch does not have to contain 1s, and the contents of the port 2 SFR are not modified. If an 8-bit address is used (MOVX @Ri), the contents of the port 2 SFR remain at the port 2 pins throughout the external memory cycle. This will facilitate paging. It should be noted that, if a port 2 pin outputs an address bit that is a 1, strong pullups will be used for the entire read/write cycle and not only for two oscillator periods.
Semiconductor Group
4-1
1997-10-01
External Bus Interface C540U / C541U
a) S1 ALE
One Machine Cycle S2 S3 S4 S5 S6 S1
One Machine Cycle S2 S3 S4 S5 S6
PSEN RD PCH OUT INST. IN PCL OUT PCL OUT valid b) S1 ALE INST. IN PCL OUT PCL OUT valid PCH OUT INST. IN PCL OUT PCL OUT valid PCH OUT INST. IN PCL OUT PCL OUT valid PCH OUT INST. IN (A) without MOVX
P2
P0
One Machine Cycle S2 S3 S4 S5 S6 S1
One Machine Cycle S2 S3 S4 S5 S6
PSEN (B) with MOVX PCH OUT INST. IN PCL OUT PCL OUT valid INST. IN DPL or Ri valid DPH OUT OR P2 OUT DATA IN PCL OUT PCL OUT valid PCH OUT INST. IN
MCT03220
RD
P2
P0
Figure 4-1 External Program Memory Execution
Semiconductor Group
4-2
1997-10-01
External Bus Interface C540U / C541U
4.1.2 Timing The timing of the external bus interface, in particular the relationship between the control signals ALE, PSEN, RD, WR and information on port 0 and port 2, is illustated in figure 4-1 a) and b). Data memory: in a write cycle, the data byte to be written appears on port 0 just before WR is activated and remains there until after WR is deactivated. In a read cycle, the incoming byte is accepted at port 0 before the read strobe is deactivated.
Program memory: Signal PSEN functions as a read strobe. 4.1.3 External Program Memory Access The external program memory is accessed under two conditions: - - whenever signal EA is active (low); or - - whenever the program counter (PC) content is greater than 7FFFH When the CPU is executing out of external program memory, all 8 bits of port 2 are dedicated to an output function and must not be used for general-purpose I/O. The content of the port 2 SFR however is not affected. During external program memory fetches port 2 lines output the high byte of the PC, and during accesses to external data memory they output either DPH or the port 2 SFR (depending on whether the external data memory access is a MOVX @DPTR or a MOVX @Ri).
4.2
PSEN, Program Store Enable
The read strobe for external program memory fetches is PSEN. It is not activated for internal program memory fetches. When the CPU is accessing external program memory, PSEN is activated twice every instruction cycle (except during a MOVX instruction) no matter whether or not the byte fetched is actually needed for the current instruction. When PSEN is activated its timing is not the same as for RD. A complete RD cycle, including activation and deactivation of ALE and RD, takes 6 oscillator periods. A complete PSEN cycle, including activation and deactivation of ALE and PSEN, takes 3 oscillator periods. The execution sequence for these two types of read cycles is shown in figure 4-1 a) and b).
4.3
Overlapping External Data and Program Memory Spaces
In some applications it is desirable to execute a program from the same physical memory that is used for storing data. In the C540U/C541U the external program and data memory spaces can be combined by the logical-AND of PSEN and RD. A positive result from this AND operation produces a low active read strobe that can be used for the combined physical memory. Since the PSEN cycle is faster than the RD cycle, the external memory needs to be fast enough to adapt to the PSEN cycle.
Semiconductor Group
4-3
1997-10-01
External Bus Interface C540U / C541U
4.4
ALE, Address Latch Enable
The main function of ALE is to provide a properly timed signal to latch the low byte of an address from P0 into an external latch during fetches from external memory. The address byte is valid at the negative transition of ALE. For that purpose, ALE is activated twice every machine cycle. This activation takes place even if the cycle involves no external fetch. The only time no ALE pulse comes out is during an access to external data memory when RD/WR signals are active. The first ALE of the second cycle of a MOVX instruction is missing (see figure 4-1 b). Consequently, in any system that does not use data memory, ALE is activated at a constant rate of 1/6 of the oscillator frequency and can be used for external clocking or timing purposes. The C540U/C541U allows to switch off the ALE output signal. If the internal ROM is used (EA=1) and ALE is switched off by EALE=0, ALE will only go active during external data memory accesses (MOVX instructions) and code memory accesses with an address greater than 0FFFH for the C540U or greater than 1FFFH for the C541U (external code memory fetches). If EA=0, the ALE generation is always enabled and the bit EALE has no effect. After a hardware reset the ALE generation is enabled. Special Function Register SYSCON (Address B1H) Bit No. MSB 7 B1H - Reset Value : XX10XXXXB LSB 0 - SYSCON
6 -
5 EALE
4 RMAP
3 -
2 -
1 -
The function of the shaded bit is not described in this section. Bit - EALE Function Not implemented. Reserved for future use. Enable ALE output EALE = 0 : ALE generation is disabled; disables ALE signal generation during internal code memory accesses (EA=1). With EA=1, ALE is automatically generated at MOVX instructions and code memory accesses with an address greater 0FFFH (C540U) or greater 1FFFH. EALE = 1 : ALE generation is enabled If EA=0, the ALE generation is always enabled and the bit EALE has no effect on the ALE generation.
Semiconductor Group
4-4
1997-10-01
External Bus Interface C540U / C541U
4.5
Enhanced Hooks Emulation Concept
The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each C500 production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensures that emulation and production chips are identical. The Enhanced Hooks TechnologyTM 1), which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break.
ICE-System Interface to Emulation Hardware
SYSCON PCON TCON
RESET EA ALE PSEN
RSYSCON RPCON RTCON
EH-IC
C500 MCU
Optional I/O Ports
Port 0 Port 2
Enhanced Hooks Interface Circuit
Port 3
Port 1
RPort 2 RPort 0
TEA TALE TPSEN
Target System Interface
MCS02647
Figure 4-2 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the programm execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU.
1)
"Enhanced Hooks Technology" is a trademark and patent of Metalink Corporation licensed to Siemens.
Semiconductor Group
4-5
1997-10-01
External Bus Interface C540U / C541U
Semiconductor Group
4-6
1997-10-01
Reset / System Clock C540U / C541U
5 5.1
Reset and System Clock Operation Hardware Reset Operation
The hardware reset function incorporated in the C540U/C541U allows for an easy automatic startup at a minimum of additional hardware and forces the controller to a predefined default state. The hardware reset function can also be used during normal operation in order to restart the device. This is particularly done when the power down mode is to be terminated. Additional to the hardware reset, which is applied externally to the device, there are two internal reset sources, the watchdog timer (C541U only) and the oscillator watchdog. This chapter deals only with the external hardware reset. The RESET input is an active high input. An internal Schmitt trigger is used at the input for noise rejection. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycles (12 oscillator periods) while the oscillator is running. With the oscillator running the internal reset is executed during the second machine cycle and is repeated every cycle until RESET goes low again. During reset, pins ALE and PSEN are configured as inputs and should not be stimulated or driven externally. (An external stimulation at these lines during reset activates several test modes which are reserved for test purposes. This in turn may cause unpredictable output operations at several port pins). At the RESET pin, a pulldown resistor is internally connected to VSS to allow a power-up reset with an external capacitor only. An automatic power-up reset can be obtained when VCC is applied by connecting the RESET pin to VCC via a capacitor. After VCC has been turned on, the capacitor must hold the voltage level at the reset pin for a specific time to effect a complete reset. The time required for a reset operation is the oscillator start-up time plus 2 machine cycles, which, under normal conditions, must be at least 10 - 20 ms for a crystal oscillator. This requirement is typically met using a capacitor of 4.7 to 10 F. The same considerations apply if the reset signal is generated externally (figure 5-1 b). In each case it must be assured that the oscillator has started up properly and that at least two machine cycles have passed before the reset signal goes inactive.
Semiconductor Group
5-1
1997-10-01
Reset / System Clock C540U / C541U
VCC
+
a) C540U C541U RESET
b) C540U C541U RESET
&
VCC
VCC
+
c) C540U C541U RESET
MCD03376
Figure 5-3 Reset Circuitries A correct reset leaves the processor in a defined state. The program execution starts at location 0000H. After reset is internally accomplished the port latches of ports 0 to 3 are set to FFH. This leaves port 0 floating, since it is an open drain port when not used as data/address bus. All other I/O port lines (ports 1 and 3) output a one (1). Port 2 lines output a zero (or one) after reset, if EA is held low (or high). The content of the internal RAM of the C540U/C541U is not affected by a reset. After power-up the content is undefined, while it remains unchanged during a reset if the power supply is not turned off. A reset operation of the USB module in the C540U/C541U can only be achieved under software control. A hardware reset operation puts only the internal CPU interface of the USB module and its MMU into a well defined reset state. The software reset, which must be executed after a hardware reset, is initiated by setting bit SWR in SFR DCR by software. Bit SWR is reset automatically by hardware when the software reset operation of the USB module is finished. Further, with the reset of bit SWR, bit DINIT in DCR is set indicating the CPU that it has to initialize the endpoints of USB module.
Semiconductor Group
5-2
1997-10-01
Reset / System Clock C540U / C541U
5.2
Fast Internal Reset after Power-On
The C540U/C541U uses the oscillator watchdog unit for a fast internal reset procedure after power-on. Figure 5-1 shows the power-on sequence under control of the oscillator watchdog. Normally the devices of the 8051 family do not enter their default reset states before the on-chip oscillator starts. The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state. Especially if a crystal is used the start up time of the oscillator is relatively long (typ. 10 ms). During this time period the pins have an undefined state which could have severe effects especially to actuators connected to port pins. In the C540U/C541U the oscillator watchdog unit avoids this situation. In this case, after power-on the oscillator watchdog's RC oscillator starts working within a very short start-up time (typ. less than 2 microseconds). In the following the watchdog circuitry detects a failure condition for the on-chip oscillator because this has not yet started (a failure is always recognized if the watchdog's RC oscillator runs faster than the on-chip oscillator). As long as this condition is detected the watchdog uses the RC oscillator output as clock source for the chip rather than the on-chip oscillator's output. This allows correct resetting of the part and brings also all ports to the defined state (see figure 5-4). Under worst case conditions (fast VCC rise time - e.g. 1 s, measured from VCC = 4.25 V up to stable port condition), the delay between power-on and the correct port reset state is : - Typ.: - Max.: 18 s 34 s
The RC oscillator will already run at a VCC below 4.0V (lower specification limit). Therefore, at slower VCC rise times the delay time will be less than the two values given above. After the on-chip oscillator has finally started, the oscillator watchdog detects the correct function; then the watchdog still holds the reset active for a time period of max. 768 cycles of the RC oscillator clock in order to allow the oscillation of the on-chip oscillator to stabilize (figure 5-4, II). Subsequently the clock is supplied by the on-chip oscillator and the oscillator watchdog's reset request is released (figure 5-4, III). However, an externally applied reset still remains active (figure 5-4, IV) and the device does not start program execution (figure 5-4, V) before the external reset is also released. Although the oscillator watchdog provides a fast internal reset it is additionally necessary to apply the external reset signal when powering up. The reasons are as follows: - - Termination of software power down mode Reset of the status flag OWDS that is set by the oscillator watchdog during the power up sequence.
Using a crystal or ceramic resonator for clock generation, the external reset signal must be held active at least until the on-chip oscillator has started and the internal watchdog reset phase is completed (after phase III in figure 5-4). When an external clock generator is used, phase II is very short. Therefore, an external reset time of typically 1 ms is sufficent in most applications. Generally, for reset time generation at power-on an external capacitor can be applied to the RESET pin.
Semiconductor Group
5-3
1997-10-01
Semiconductor Group 5-4 1997-10-01
Figure 5-4 Power-On Reset of the C541U
Ports
Undef.
RESET
On-Chip Osc.
RC Osc.
V CC
RESET
Clock from RC-Oscillator; RESET at Ports
On-Chip Osc. starts; Final RESET Sequence by Osc.-WD; (max. 768 RC Clock Cycles)
V
Port remains in RESET because of active ext. RESET Signal
V
Reset / System Clock C540U / C541U
Power On; undef. Ports typ. 18 s max. 34 s
Start of Program Execution
MCT02627
Reset / System Clock C540U / C541U
5.3
Hardware Reset Timing
This section describes the timing of the hardware RESET signal. The input pin RESET is sampled once during each machine cycle. This happens in state 5 phase 2. Thus, the external reset signal is synchronized to the internal CPU timing. When RESET is found active (high level) the internal reset procedure is started. It needs two complete machine cycles to put the complete device to its correct reset state, i.e. all special function registers contain their default values, the port latches contain 1's etc. Note that this reset procedure is also performed if there is no clock available at the device. (This is done by the oscillator watchdog, which provides an auxiliary clock for performing a perfect reset without clock at the XTAL1 and XTAL2 pins). The RESET signal must be active for at least two machine cycles; after this time the C540U/C541U remains in its reset state as long as the signal is active. When the signal goes inactive this transition is recognized in the following state 5 phase 2 of the machine cycle. Then the processor starts its address output (when configured for external program memory) in the following state 5 phase 1. One phase later (state 5 phase 2) the first falling edge at pin ALE occurs. Figure 5-5 shows this timing for a configuration with EA = 0 (external program memory). Thus, between the release of the RESET signal and the first falling edge at ALE there is a time period of at least one machine cycle but less than two machine cycles.
One Machine Cycle S4 S5 S6 S1 P1 P2 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2
RESET
P0
PCL OUT PCH OUT
Inst. in
PCL OUT PCH OUT
P2
ALE
MCT02092
Figure 5-5 CPU Timing after Reset
Semiconductor Group
5-5
1997-10-01
Reset / System Clock C540U / C541U
5.4
Oscillator and Clock Circuit
The oscillator and clock generation circuitry of the C540U/C541U is shown in figure 5-6. The crystal oscillator generates the system clock for the microcontroller. The USB module can be provided with the following clocks : - Full speed operation : 48 MHz with a data rate of 12 Mbit/s - Low speed operation : 6 MHz with a data rate of 1.5 Mbit/s The low speed clock is generated by a dividing the system clock by 2. The full speed clock is generated by a PLL, which multiplies the system clock by a fix factor of 4. This PLL can be enabled or disabled by bit PCLK of SFR DCR. Depending on full or low speed operation of the USB bit SPEED of SFR has to be set or cleared for the selection of the USB clock. Bit UCLK is a general enable bit for the USB clock.
XTAL1 12 MHz XTAL2
Pin Pin
Crystal 12 MHz Oscillator
System Clock of the Microcontroler
Divider by 2 6 MHz
PLL x4 48 MHz 1 0
Enable
PCLK DCR.0
to USB Module SPEED DCR.7 UCLK DCR.1
MCB03377
C540U / C541U
Figure 5-6 Block Diagram of the Clock Generation Circuitry In low speed mode the PLL is not required. Therefore, the PLL should be always disabled in low speed mode. This also reduces the power consumption and the EMC of the C540U/C541U when used in low speed mode. Note: For correct function of the USB module the C540U/C541U must operate with 12 MHz external clock. The microcontroller (except the USB module) is capaable to operate down to 2 MHz
Semiconductor Group
5-6
1997-10-01
Reset / System Clock C540U / C541U
After a hardware reset operation bits PCLK, SPEED, and UCLK are set to 0. Depending on the required operating mode of the USB module a well defined procedure must be executed for switching on the clock for the USB module : - Full speed mode USB PLL is switched on by setting bit PCLK waiting 3 ms for PLL being locked setting bit UCLK setting bit UCLK only
- Low speed mode
The switch-on procedure after hardware reset assures a proper operation of the USB clock system. A software reset operation of the USB module must follow this clock system switch-on procedure. Details of the software reset operation are described in chapter 6.??.
XTAL1 and XTAL2 are the input and output of a single-stage on-chip inverter which can be configured with off-chip components as a Pierce oscillator. The oscillator, in any case, drives the internal clock generator. The clock generator provides the internal clock signals to the chip. These signals define the internal phases, states and machine cycles. Figure 5-7 shows the recommended oscillator circuit.
C XTAL2 C540U C541U XTAL1 C = 20 pF 10 pF for crystal operation
MCS03424
12 MHz C
Figure 5-7 Recommended Crystal Oscillator Circuit In this application the on-chip oscillator is used as a crystal-controlled, positive-reactance oscillator (a more detailed schematic is given in figure 5-8). lt operates in fundamental response mode as an inductive reactor in parallel resonance with a capacitor external to the chip. The crystal specifications and capacitances are non-critical. In this circuit 20 pF can be used as single capacitance at any frequency together with a good quality crystal.
Semiconductor Group
5-7
1997-10-01
Reset / System Clock C540U / C541U
To Internal Timing Circuitry
XTAL2 12 MHz
XTAL1
C540U C541U
C1
C2
MCD03395
Figure 5-8 On-Chip Oscillator Circuiry To drive the C540U/C541U with an external clock source, the external clock signal has to be applied to XTAL1, as shown in figure 5-9. XTAL2 has to be left unconnected. A pullup resistor is suggested (to increase the noise margin), but is optional if VOH of the driving gate corresponds to the VIH2 specification of XTAL1.
V CC
N.C.
C540U C541U XTAL2
External Clock Signal
XTAL1
MCD03396
Figure 5-9 External Clock Source
Semiconductor Group
5-8
1997-10-01
On-Chip Peripheral Components C540U / C541U
6
On-Chip Peripheral Components
This chapter gives detailed information about all on-chip peripherals of the C540U/C541U except for the integrated interrupt controller, which is described separately in chapter 7. 6.1 Parallel I/O
The C540U/C541U in the P-SDIP-52 package has four 8-bit I/O ports. In the P-LCC-44 package port 1 is a 6-bit I/O port only. Port 0 is an open-drain bidirectional I/O port, while ports 1 to 3 are quasi-bidirectional I/O ports with internal pullup resistors. That means, when configured as inputs, ports 1 to 3 will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input. The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. In this application, port 0 outputs the low byte of the external memory address, time multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR contents. In this function, port 0 is not an open-drain port, but uses a strong internal pullup FET. Two port lines of port 1 (P1.0/LED0, P1.1/LED1) and one port line of port 3 (P3.0/LED2) have the capability of driving external LEDs in the output low state.
Semiconductor Group
6-1
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.1.1 Port Structures The C540U/C541U allows for digital I/O on 30 lines (P-LCC-44) or 32 lines (P-SDIP-52) grouped into 4 bidirectional 8-/6-bit ports. Each port bit consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0 through P3 are performed via their corresponding special function registers P0 to P3. Figure 6-1 shows a functional diagram of a typical bit latch and I/O buffer, which is the core of each of the 4 I/O-ports. The bit latch (one bit in the port's SFR) is represented as a type-D flip-flop, which will clock in a value from the internal bus in response to a "write-to-latch" signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a "read-latch" signal from the CPU. The level of the port pin itself is placed on the internal bus in response to a "read-pin" signal from the CPU. Some instructions that read from a port (i.e. from the corresponding port SFR P0 to P3) activate the "read-latch" signal, while others activate the "read-pin" signal.
Read Latch
Int. Bus Write to Latch
D Port Latch CLK
Q Port Driver Circuit Port Pin
Q
MCS01822
Read Pin
Figure 6-10 Basic Structure of a Port Circuitry
Semiconductor Group
6-2
1997-10-01
On-Chip Peripheral Components C540U / C541U
Port 1, 2 and 3 output drivers have internal pullup FET's (see figure 6-11). Each I/O line can be used independently as an input or output. To be used as an input, the port bit stored in the bit latch must contain a one (1) (that means for figure 6-11: Q=0), which turns off the output driver FET n1. Then, for ports 1, 2 and 3, the pin is pulled high by the internal pullups, but can be pulled low by an external source. When externally pulled low the port pins source current (IIL or ITL). For this reason these ports are sometimes called "quasi-bidirectional".
Read Latch
VCC
Internal Pull Up Arrangement Q Bit Latch CLK Pin
Int. Bus Write to Latch
D
Q
n1
MCS01823
Read Pin
Figure 6-11 Basic Output Driver Circuit of Ports 1, 2, and 3
Semiconductor Group
6-3
1997-10-01
On-Chip Peripheral Components C540U / C541U
In fact, the pullups mentioned before and included in figure 6-11 are pullup arrangements as shown in figure 6-12. One n-channel pulldown FET and three pullup FETs are used:
Delay = 1 State
VCC
=1
_ <1
p1
p2
p3 Port Pin
Q
n1
VSS
Input Data (Read Pin) =1 =1
MCS03230
Figure 6-12 Output Driver Circuit of Ports 1 to 5 and 7 - The pulldown FET n1 is of n-channel type. It is a very strong driver transistor which is capable of sinking high currents (IOL); it is only activated if a "0" is programmed to the port pin. A short circuit to VCC must be avoided if the transistor is turned on, since the high current might destroy the FET. This also means that no "0" must be programmed into the latch of a pin that is used as input. - The pullup FET p1 is of p-channel type. It is activated for 1 state (S1) if a 0-to-1 transition is programmed to the port pin, i.e. a "1" is programmed to the port latch which contained a "0". The extra pullup can drive a similar current as the pulldown FET n1. This provides a fast transition of the logic levels at the pin. - The pullup FET p2 is of p-channel type. It is always activated when a "1" is in the port latch, thus providing the logic high output level. This pullup FET sources a much lower current than p1; therefore the pin may also be tied to ground, e.g. when used as input with logic low input level. - The pullup FET p3 is of p-channel type. It is only activated if the voltage at the port pin is higher than approximately 1.0 to 1.5 V. This provides an additional pullup current if a logic high level shall be output at the pin (and the voltage is not forced lower than approximately 1.0 to 1.5 V). However, this transistor is turned off if the pin is driven to a logic low level, e.g when used as input. In this configuration only the weak pullup FET p2 is active, which sources the current IIL . If, in addition, the pullup FET p3 is activated, a higher current can be sourced (ITL). Thus, an additional power consumption can be avoided if port pins are used as inputs with a low level applied. However, the driving capability is stronger if a logic high level is output.
Semiconductor Group
6-4
1997-10-01
On-Chip Peripheral Components C540U / C541U
The described activating and deactivating of the four different transistors results in four states which can be : - - - - input low state (IL), p2 active only input high state (IH) = steady output high state (SOH), p2 and p3 active forced output high state (FOH), p1, p2 and p3 active output low state (OL), n1 active
If a pin is used as input and a low level is applied, it will be in IL state, if a high level is applied, it will switch to IH state. If the latch is loaded with "0", the pin will be in OL state. If the latch holds a "0" and is loaded with "1", the pin will enter FOH state for two cycles and then switch to SOH state. If the latch holds a "1" and is reloaded with a "1" no state change will occur. At the beginning of power-on reset the pins will be in IL state (latch is set to "1", voltage level on pin is below of the trip point of p3). Depending on the voltage level and load applied to the pin, it will remain in this state or will switch to IH (=SOH) state. If it is is used as output, the weak pull-up p2 will pull the voltage level at the pin above p3's trip point after some time and p3 will turn on and provide a strong "1". Note, however, that if the load exceeds the drive capability of p2 (IIL), the pin might remain in the IL state and provide a week "1" until the first 0-to-1 transition on the latch occurs. Until this the output level might stay below the trip point of the external circuitry. The same is true if a pin is used as bidirectional line and the external circuitry is switched from output to input when the pin is held at "0" and the load then exceeds the p2 drive capabilities. If the load exceeds IIL the pin can be forced to "1" by writing a "0" followed by a "1" to the port pin..
Semiconductor Group
6-5
1997-10-01
On-Chip Peripheral Components C540U / C541U
Port 0, in contrast to ports 1, 2 and 3, is considered as "true" bidirectional, because the port 0 pins float when configured as inputs. Thus, this port differs in not having internal pullups. The pullup FET in the P0 output driver (see figure 6-13) is used only when the port is emitting 1 s during the external memory accesses. Otherwise, the pullup is always off. Consequently, P0 lines that are used as output port lines are open drain lines. Writing a "1" to the port latch leaves both output FETs off and the pin floats. In that condition it can be used as high-impedance input. If port 0 is configured as general I/O port and has to emit logic high-level (1), external pullups are required.
Addr./Data Read Latch Control &
VCC
=1 Int. Bus Write to Latch D Bit Latch CLK Q
Port Pin
Q
MUX
MCS02122
Read Pin
Figure 6-13 Port 0 Circuitry
Semiconductor Group
6-6
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.1.1.1
Port 0 and Port 2 used as Address/Data Bus
As shown in figure 6-13 and below in figure 6-14, the output drivers of ports 0 and 2 can be switched to an internal address or address/data bus for use in external memory accesses. In this application they cannot be used as general purpose I/O, even if not all address lines are used externally. The switching is done by an internal control signal dependent on the input level at the EA pin and/or the contents of the program counter. If the ports are configured as an address/data bus, the port latches are disconnected from the driver circuit. During this time, the P2 SFR remains unchanged while the P0 SFR has 1's written to it. Being an address/data bus, port 0 uses a pullup FET as shown in figure 6-13. When a 16-bit address is used, port 2 uses the additional strong pullups p1 to emit 1's for the entire external memory cycle instead of the weak ones (p2 and p3) used during normal port activity.
Read Latch Addr. Control
V CC
Internal Pull Up Arrangement
Int. Bus Write to Latch
D Bit Latch CLK
Q MUX Q =1
Port Pin
Read Pin
MCS02123
Figure 6-14 Port 2 Circuitry
Semiconductor Group
6-7
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.1.2
Alternate Functions
The pins of ports 1 and 3 are multifunctional. They are port pins and also serve to implement special features as listed in table 6-5. Figure 6-15 shows a functional diagram of a port latch with alternate function. To pass the alternate function to the output pin and vice versa, however, the gate between the latch and driver circuit must be open. Thus, to use the alternate input or output functions, the corresponding bit latch in the port SFR has to contain a one (1); otherwise the pulldown FET is on and the port pin is stuck at 0. After reset all port latches contain ones (1).
Read Latch
Alternate Output Function
VCC
Internal Pull Up Arrangement Pin
Int. Bus Write to Latch
D Bit Latch CLK
Q
&
Q
MCS01827
Read Pin
Alternate Input Function
Figure 6-15 Circuitry of Ports 1 and 3
Semiconductor Group
6-8
1997-10-01
On-Chip Peripheral Components C540U / C541U
Ports 1 and 3 are provided for several alternate functions, as listed in table 6-5: Table 6-5 Alternate Functions of Port 1 and 3 Port P1.0 P1.1 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Pin T2 T2EX RxD TxD INT0 INT1 T0 T1 WR RD Alternate Function Input to counter 2 Capture-reload trigger of timer 2 / up down count Serial port's receiver data input (asynchronous) or data input/output (synchronous) Serial port's transmitter data output (asynchronous) or data clock output (synchronous) External interrupt 0 input, timer 0 gate control External interrupt 1 input, timer 1 gate control Timer 0 external counter input Timer 1 external counter input External data memory write strobe External data momory read strobe
Semiconductor Group
6-9
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.1.3 Port Handling 6.1.3.1 Port Timing
When executing an instruction that changes the value of a port latch, the new value arrives at the latch during S6P2 of the final cycle of the instruction. However, port latches are only sampled by their output buffers during phase 1 of any clock period (during phase 2 the output buffer holds the value it noticed during the previous phase 1). Consequently, the new value in the port latch will not appear at the output pin until the next phase 1, which will be at S1P1 of the next machine cycle. When an instruction reads a value from a port pin (e.g. MOV A, P1) the port pin is actually sampled in state 5 phase 1 or phase 2 depending on port and alternate functions. Figure 6-16 illustrates this port timing. lt must be noted that this mechanism of sampling once per machine cycle is also used if a port pin is to detect an "edge", e.g. when used as counter input. In this case an "edge" is detected when the sampled value differs from the value that was sampled the cycle before. Therefore, there must be met certain requirements on the pulse length of signals in order to avoid signal "edges" not being detected. The minimum time period of high and low level is one machine cycle, which guarantees that this logic level is noticed by the port at least once.
S4 P1 P2 XTAL2
S5 P1 P2
S6 P1 P2
S1 P1 P2
S2 P1 P2
S3 P1 P2
Input sampled: e.g.: MOV A, P1 or
P1 Active (driver Transistor)
Port
Old Data
New Data
MCT03397
Figure 6-16 Port Timing
Semiconductor Group
6-10
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.1.3.2
Port Loading and Interfacing
The output buffers of ports 1, 2 and 3 can drive TTL inputs directly. The maximum port load which still guarantees correct logic output levels can be looked up in the C540U/C541U DC characteristics in chapter 10. The corresponding parameters are VOL and VOH. The same applies to port 0 output buffers. They do, however, require external pullups to drive floating inputs, except when being used as the address/data bus. When used as inputs it must be noted that the ports 1, 2 and 3 are not floating but have internal pullup transistors. The driving devices must be capable of sinking a sufficient current if a logic low level shall be applied to the port pin (the parameters I TL and I IL in the C540U/C541U DC characteristics specify these currents). Port 0 has floating inputs when used for digital input.
Semiconductor Group
6-11
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.1.3.3
Read-Modify-Write Feature of Ports 1,2 and 3
Some port-reading instructions read the latch and others read the pin. The instructions reading the latch rather than the pin read a value, possibly change it, and then rewrite it to the latch. These are called "read-modify-write"- instructions, which are listed in table 6-6. If the destination is a port or a port pin, these instructions read the latch rather than the pin. Note that all other instructions which can be used to read a port, exclusively read the port pin. In any case, reading from latch or pin, respectively, is performed by reading the SFR P0, P1, P2 and P3; for example, "MOV A, P3" reads the value from port 3 pins, while "ANL P3, #0AAH" reads from the latch, modifies the value and writes it back to the latch. It is not obvious that the last three instructions in table 6-6 are read-modify-write instructions, but they are. The reason is that they read the port byte, all 8 bits, modify the addressed bit, then write the complete byte back to the latch. Table 6-6 Read-Modify-Write"- Instructions Instruction ANL ORL XRL JBC CPL INC DEC DJNZ MOV Px.y,C CLR Px.y SETB Px.y Function Logic AND; e.g. ANL P1, A Logic OR; e.g. ORL P2, A Logic exclusive OR; e.g. XRL P3, A Jump if bit is set and clear bit; e.g. JBC P1.1, LABEL Complement bit; e.g. CPL P3.0 Increment byte; e.g. INC P1 Decrement byte; e.g. DEC P1 Decrement and jump if not zero; e.g. DJNZ P3, LABEL Move carry bit to bit y of port x Clear bit y of port x Set bit y of port x
The reason why read-modify-write instructions are directed to the latch rather than the pin is to avoid a possible misinterpretation of the voltage level at the pin. For example, a port bit might be used to drive the base of a transistor. When a "1" is written to the bit, the transistor is turned on. If the CPU then reads the same port bit at the pin rather than the latch, it will read the base voltage of the transistor (approx. 0.7 V, i.e. a logic low level!) and interpret it as "0". For example, when modifying a port bit by a SETB or CLR instruction, another bit in this port with the above mentioned configuration might be changed if the value read from the pin were written back to the latch. However, reading the latch rater than the pin will return the correct value of "1".
Semiconductor Group
6-12
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.2
Timers/Counters
The C540U/C541U contains two 16-bit timers/counters, timer 0 and 1, which are useful in many applications for timing and counting. In "timer" function, the timer register is incremented every machine cycle. Thus one can think of it as counting machine cycles. Since a machine cycle consists of 6 oscillator periods, the counter rate is 1/6 of the oscillator frequency. In "counter" function, the timer register is incremented in response to a 1-to-0 transition (falling edge) at its corresponding external input pin, T0 or T1 (alternate functions of P3.4 and P3.5). In this function the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since it takes two machine cycles (12 oscillator periods) to recognize a 1-to-0 transition, the maximum count rate is 1/12 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for at least one full machine cycle.
6.2.1
Timer/Counter 0 and 1
Timer / counter 0 and 1 of the C540U/C541U are fully compatible with timer / counter 0 and 1 of the 80C51/C501 and can be used in the same four operating modes: Mode 0: 8-bit timer/counter with a divide-by-32 prescaler Mode 1: 16-bit timer/counter Mode 2: 8-bit timer/counter with 8-bit auto-reload Mode 3: Timer/counter 0 is configured as one 8-bit timer/counter and one 8-bit timer; Timer/ counter 1 in this mode holds its count. The effect is the same as setting TR1 = 0. External inputs INT0 and INT1 can be programmed to function as a gate for timer/counters 0 and 1 to facilitate pulse width measurements. Each timer consists of two 8-bit registers (TH0 and TL0 for timer/counter 0, TH1 and TL1 for timer/ counter 1) which may be combined to one timer configuration depending on the mode that is established. The functions of the timers are controlled by two special function registers TCON and TMOD. In the following descriptions the symbols TH0 and TL0 are used to specify the high-byte and the low-byte of timer 0 (TH1 and TL1 for timer 1, respectively). The operating modes are described and shown for timer 0. If not explicity noted, this applies also to timer 1.
Semiconductor Group
6-13
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.2.1.1
Timer/Counter 0 and 1 Registers
Totally six special function registers control the timer/counter 0 and 1 operation : - TL0/TH0 and TL1/TH1 - counter registers, low and high part - TCON and TMOD - control and mode select registers Special Function Register TL0 (Address 8AH) Special Function Register TH0 (Address 8CH) Special Function Register TL1 (Address 8BH) Special Function Register TH1 (Address 8DH) Bit No. MSB 7 .7 Reset Value : 00H Reset Value : 00H Reset Value : 00H Reset Value : 00H LSB 0 .0 TL0
6 .6
5 .5
4 .4
3 .3
2 .2
1 .1
8AH
8CH
.7
.6
.5
.4
.3
.2
.1
.0
TH0
8BH
.7
.6
.5
.4
.3
.2
.1
.0
TL1
8DH
.7
.6
.5
.4
.3
.2
.1
.0
TH1
Bit TLx.7-0 x=0-1
Function Timer/counter 0/1 low value Operating Mode Description 0 1 2 3 "TLx" holds the 5-bit prescaler value. "TLx" holds the lower 8-bit part of the 16-bit timer/counter value. "TLx" holds the 8-bit timer/counter value. TL0 holds the 8-bit timer/counter value; TL1 is not used.
THx.7-0 x=0-1
Timer/counter 0/1 high value Operating Mode Description 0 1 2 3 "THx" holds the 8-bit timer/counter value. "THx" holds the higher 8-bit part of the 16-bit timer/counter value "THx" holds the 8-bit reload value. TH0 holds the 8-bit timer value; TH1 is not used.
Semiconductor Group
6-14
1997-10-01
On-Chip Peripheral Components C540U / C541U
Special Function Register TCON (Address 88H) Bit No. MSB 7 8FH 88H TF1 6 8EH TR1 5 8DH TF0 4 8CH TR0 3 8BH IE1 2 8AH IT1 1 89H IE0
Reset Value : 00H LSB 0 88H IT0 TCON
The shaded bits are not used for controlling timer/counter 0 and 1.
Bit TR0 TF0
Function Timer 0 run control bit Set/cleared by software to turn timer/counter 0 ON/OFF. Timer 0 overflow flag Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 1 run control bit Set/cleared by software to turn timer/counter 1 ON/OFF. Timer 1 overflow flag Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine.
TR1 TF1
Semiconductor Group
6-15
1997-10-01
On-Chip Peripheral Components C540U / C541U
Special Function Register TMOD (Address 89H) Bit No. 89H MSB 7 Gate
Reset Value : 00H LSB 0 M0 TMOD
6 C/T
5 M1
4 M0
3 Gate
2 C/T
1 M1
Timer 1 Control
Timer 0 Control
Bit GATE
Function Timer 1/0 gating control When set, timer/counter "x" is enabled only while "INT x" pin is high and "TRx" control bit is set. When cleared timer "x" is enabled whenever "TRx" control bit is set. Timer 1/0 counter or timer select bit Set for counter operation (input from "Tx" input pin). Cleared for timer operation (input from internal system clock). Timer 1/0 mode select bits M1 0 M0 0 Function 8-bit timer/counter: "THx" operates as 8-bit timer/counter "TLx" serves as 5-bit prescaler 16-bit timer/counter. "THx" and "TLx" are cascaded; there is no prescaler 8-bit auto-reload timer/counter. "THx" holds a value which is to be reloaded into "TLx" each time it overflows Timer 0 : TL0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. TH0 is an 8-bit timer only controlled by timer 1 control bits. Timer 1 : Timer/counter 1 stops
C/T
M1 M0
0 1
1 0
1
1
Semiconductor Group
6-16
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.2.1.2
Mode 0
Putting either timer/counter 0,1 into mode 0 configures it as an 8-bit timer/counter with a divide-by32 prescaler. Figure 6-17 shows the mode 0 operation. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1's to all 0's, it sets the timer overflow flag TF0. The overflow flag TF0 then can be used to request an interrupt. The counted input is enabled to the timer when TR0 = 1 and either Gate = 0 or INT0 = 1 (setting Gate = 1 allows the timer to be controlled by external input INT0, to facilitate pulse width measurements). TR0 is a control bit in the special function register TCON; Gate is in TMOD. The 13-bit register consists of all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3 bits of TL0 are indeterminate and should be ignored. Setting the run flag (TR0) does not clear the registers. Mode 0 operation is the same for timer 0 as for timer 1. Substitute TR0, TF0, TH0, TL0 and INT0 for the corresponding timer 1 signals in figure 6-17. There are two different gate bits, one for timer 1 (TMOD.7) and one for timer 0 (TMOD.3).
OSC
/6 C/T = 0 TL0 (5 Bits) C/T = 1 TH0 (8 Bits) TF0 Interrupt
P3.4/T0 Control Gate =1
_ <1
TR0
&
P3.2/INT0
MCS02726
Figure 6-17 Timer/Counter 0, Mode 0: 13-Bit Timer/Counter
Semiconductor Group
6-17
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.2.1.3
Mode 1
Mode 1 is the same as mode 0, except that the timer register is running with all 16 bits. Mode 1 is shown in figure 6-18.
OSC
/6 C/T = 0 TL0 (8 Bits) C/T = 1 TH0 (8 Bits) TF0 Interrupt
P3.4/T0 Control Gate =1
_ <1
TR0
&
P3.2/INT0
MCS02727
Figure 6-18 Timer/Counter 0, Mode 1: 16-Bit Timer/Counter
Semiconductor Group
6-18
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.2.1.4
Mode 2
Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in figure 6-19. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which is preset by software. The reload leaves TH0 unchanged.
OSC
/6 C/T = 0 TL0 (8 Bits) C/T = 1 TF0 Interrupt
P3.4/T0 Control Gate =1
_ <1
Reload
TR0
& TH0 (8 Bits)
MCS02728
P3.2/INT0
Figure 6-19 Timer/Counter 0,1, Mode 2: 8-Bit Timer/Counter with Auto-Reload
Semiconductor Group
6-19
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.2.1.5
Mode 3
Mode 3 has different effects on timer 0 and timer 1. Timer 1 in mode 3 simply holds its count. The effect is the same as setting TR1=0. Timer 0 in mode 3 establishes TL0 and TH0 as two seperate counters. The logic for mode 3 on timer 0 is shown in figure 6-20. TL0 uses the timer 0 control bits: C/T, Gate, TR0, INT0 and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from timer 1. Thus, TH0 now controls the "timer 1" interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer or counter. When timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or can still be used by the serial channel as a baud rate generator, or in fact, in any application not requiring an interrupt from timer 1 itself.
OSC
/6
f OSC /6
C/T = 0
Timer Clock TL0 (8 Bits)
TF0
Interrupt
C/T = 1 P3.4/T0 =1
_ <1
Control TR0 &
Gate
P3.2/INT0 TH0 (8 Bits) TR1
TR1
TF1
Interrupt
MCS02729
Figure 6-20 Timer/Counter 0, Mode 3: Two 8-Bit Timers/Counters
Semiconductor Group
6-20
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.3
SSC Interface (C541U only)
The C541U microcontroller provides a Synchronous Serial Channel unit, the SSC. This interface is compatible to the popular SPI serial bus interface. It can be used for simple I/O expansion via shift registers, for connection of a variety of peripheral components, such as A/D converters, EEPROMs etc., or for allowing several microcontrollers to be interconnected in a master/slave structure. It supports full-duplex or half-duplex operation and can run in a master or a slave mode. Figure 6-21 shows the block diagram of the SSC. The central element of the SSC is an 8-bit shift register. The input and the output of this shift register are each connected via a control logic to the pin P1.3 / SRI (SSC Receiver In) and P1.4 / STO (SSC Transmitter Out). This shift register can be written to (SFR STB) and can be read through the Receive Buffer Register SRB.
Pin
P1.2 / SCLK
f OSC
Pin Clock Divider ... Clock Selection Shift Register SRB Receive Buffer Register Interrupt Pin P1.5 / SLS STB Pin Control Logic P1.3 / SRI
Pin
P1.4 / STO
SCIEN Int. Enable Reg. SSCCON Control Register Status Register Control Logic SCF
Internal Bus
MCB03379
Figure 6-21 SSC Block Diagram
Semiconductor Group
6-21
1997-10-01
On-Chip Peripheral Components C540U / C541U
As the SSC is a synchronous serial interface, for each transfer a dedicated clock signal sequence must be provided. The SSC has implemented a clock control circuit, which can generate the clock via a baud rate generator in the master mode, or receive the transfer clock in the slave mode. The clock signal is fully programmable for clock polarity and phase. The pin used for the clock signal is P1.2 / SCLK. When operating in slave mode, a slave select input SLS is provided which enables the SSC interface and also will control the transmitter output. The pin used for this is P1.5 / SLS. In addition to this there is an additional option for controlling the transmitter output by software. The SSC control block is responsible for controlling the different modes and operation of the SSC, checking the status, and generating the respective status and interrupt signals. 6.3.1 General Operation of the SSC After initialization of the SSC, the data to be transmitted has to be written into the shift register STB. In master mode this will initiate the transfer by resetting the baudrate generator and starting the clock generation. The control bits CPOL and CPHA in the SSCCON register determine the idle polarity of the clock (polarity between transfers) and which clock edges are used for shifting and sampling data (see figure 6-23). While the transmit data in the shift register is shifted out bit per bit starting with the MSB or LSB, the incoming receive data are shifted in, synchronized with the clock signal at pin SCLK. When the eight bits are shifted out (and the same number is of course shifted in), the contents of the shift register is transferred to the receive buffer register SRB, and the transmission complete flag TC is set. If enabled an interrupt request will be generated. After the last bit has been shifted out and was stable for one bit time, the STO output will be switched to "1" (forced "1"), the idle state of STO. This allows connection of standard asynchronous receivers to the SSC in master mode. In slave mode the device will wait for the slave select input SLS to be activated (=low) and then will shift in the data provided on the receive input according to the clock provided at the SCLK input and the setting of the CPOL ad CPHA bits. After eight bits have been shifted in, the content of the shift register is transferred to the receive buffer register and the transmission complete flag TC is set. If the transmitter is enabled in slave mode (TEN bit set to 1), the SSC will shift out at STO at the same time the data currently contained in the shift register. If the transmitter is disabled, the STO output will remain in the tristate state. This allows more than one slave to share a common select line. If SLS is inactive the SSC will be inactive and the content of the shift register will not be modified. 6.3.2 Enable/Disable Control Bit SSCEN of the SSCCON register globally enables or disables the synchronous serial interface. Setting SSCEN to "0" stops the baud rate generator and all internal activities of the SSC. Current transfers are aborted. The alternate output functions at pins P1.3 / SRI, P1.4 / STO, P1.5 / SLS, and P1.2 / SCLK return to their primary I/O port function. These pins can now be used for general purpose I/O.
Semiconductor Group
6-22
1997-10-01
On-Chip Peripheral Components C540U / C541U
When the SSC is enabled and in master mode, pins P1.3 / SRI, P1.4 / STO, and P1.2 / SCLK will be switched to the SSC control function. P1.4 / STO and P1.2 / SCLK actively will drive the lines P1.5 / SLS will remain a regular I/O pin. The output latches of port pins dedicated to alternate functions must be programmed to logic 1 (= state after reset). In slave mode all four control pins will be switched to the alternate function. However, STO will stay in the tristate state until the transmitter is enabled by SLS input being low and the TEN control bit is set to 1. This allows for more than one slave to be connected to one select line and the final selection of the slave will be done by a software protocol. 6.3.3 Baudrate Generation (Master Mode only) The baudrate clock is generated out of the processor clock (fosc). This clock is fed into a resetable divider with seven outputs for different baudrate clocks (fosc/4 to fosc/256). One of these eight clocks is selected by the bits BRS2,1,0 in SSCCON and provided to the shift control logic. Whenever the shift register is loaded with a new value, the baudrate generation is restarted with the trailing edge of the write signal to the shift register. In the case of CPHA = 0 the baudrate generator will be restarted in a way, that the first SCLK clock transisition will not occur before one half transmit clock cycle time after the register load. This ensures that there is sufficient setup time between MSB or LSB valid on the data output and the first sample clock edge and that the MSB or LSB has the same length than the other bits. (No special care is necessary in case of CPHA=1, because here the first clock edge will be used for shifting). 6.3.4 Write Collision Detection When an attempt is made to write data to the shift register while a transfer is in progress, the WCOL bit in the status register will be set. The transfer in progress continues uninterrupted, the write will not access the shift register and will not corrupt data. However, the data written erroneously will be stored in a shadow register and can be read by reading the STB register. Depending on the operation mode there are different definitions for a transfer being considered to be in progress: Master Mode : CPHA=0: CPHA=1: from the trailing edge of the write into STB until the last sample clock edge from the first SCLK clock edge until the last sample clock edge
Note, that this also means, that writing new data into STB immediately after the transfer complete flag has been set (also initiated with the last sample clock edge) will not generate a write collision. However, this may shorten the length of the last bit (especially at slow baudrates) and prevent STO from switching to the forced "1" between transmissions. Slave Mode : CPHA=0: CPHA=1: while SLS is active from the first SCLK clock edge until the last sample clock edge
Semiconductor Group
6-23
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.3.5 Master/Slave Mode Selection The selection whether the SSC operates in master mode or in slave mode has to be made depending on the hardware configuration before the SSC will be enabled. Normally a specific device will operate either as master or as slave unit. The SSC has no on-chip support for multimaster configurations (switching between master and slave mode operation). Operating the SSC as a master in a multimaster environment requires external circuitry for swapping transmit and receive lines.
Figure 6-22 Typical SSC System Configuration
Semiconductor Group
6-24
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.3.6 Data/Clock Timing Relationships The SSC provides four different clocking schemes for clocking the data in and out of the shift register. Controlled by two bits in SSCCON, the clock polarity (idle state of the clock, control register bit CPOL) and the clock/data relationship (phase control, control register bit CPHA), i.e. which clock edges will be used for sample and shift. The following figures show the various possibilities. 6.3.6.1 Master Mode Operation
Figure 6-23 shows the clock/data/control relationship of the SSC in master mode. When CPHA is set to 1, the MSB (or LSB) of the data that was written into the shift register will be provided on the transmitter output after the first clock edge, the receiver input will sample with the next clock edge. The direction (rising or falling) of the respective clock edge is depending on the clock polarity selected. After the last bit has been shifted out, the data output STO will go to the high output level (logic 1) and remain there until the next transmission is started. However, when enabling the SSC after reset, the logic level of STO will be undefined, until the first transmission starts. When CPHA is 0, the MSB (or LSB) will output immediately after the data was written into the shift register. The first clock edge of SCLK will be used for sampling the input data, the next to shift out the next bit. Between transmissons the data output STO will be "1".
SCLK (CPOL = 0) SCLK (CPOL = 1) CPHA = 0 Write to STB Register STO Input Sample at SRI CPHA = 1 Write to STB Register STO Input Sample at SRI
MCS02440
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1) MSB shift first mode is assumed (Bit LSBSM in register SCCMOD is 0)
Figure 6-23 Master Mode Operation of SSC
Semiconductor Group
6-25
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.3.6.2
Slave Mode Operation
Figure 6-24 shows the clock/data/control relationship of the SSC in slave mode. When SLS is active (low) and CPHA is 1, the MSB (or LSB) of the data that was written into the shift register will be provided on the transmitter output after the first clock edge (if the transmitter was enabled by setting the TEN bit to 1), the receiver input will sample the input data with the next clock edge. The direction (rising or falling) of the respective clock edge is depending on the clock polarity selected. In this case (CPHA = 1) the SLS input may stay active during the transmission of consecutive bytes. When CPHA = 0 and the transmitter is enabled, the MSB (or LSB) of the shift register is provided immediately after the SLS input is pulled to active state (low). The receiver will sample the input with the first clock edge, and the transmitter will shift out the next bit with the following clock edge. If the transmitter is disabled the output will remain in the high impedance state. In this case (CPHA=0), correct operation requires that the SLS input to go inactive between consecutive bytes. When SLS is inactive the internal shift clock is disabled and the content of the shift register will not be modified. This also means that SLS must stay active until the transmission is completed. If during a transmission SLS goes inactive before all eight bits are received, the reception process will be aborted and the internal frame counter will be reset. TC will not be set in this case. With the next activation of SLS a new reception process will be started.
SCLK (CPOL = 0) SCLK (CPOL = 1)
SLS
CPHA = 1
STO Input Sample at SRI
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SLS
CPHA = 0
STO Input Sample at SRI
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MCS02441
1) MSB shift first mode is assumed (Bit LSBSM in register SCCMOD is 0)
Figure 6-24 Slave Mode Operation of SSC Semiconductor Group 6-26 1997-10-01
On-Chip Peripheral Components C540U / C541U
6.3.7 Register Description The SSC interface has six SFRs which are listed in table 6-7. Table 6-7 Special Function Registers of the COMP Unit Symbol SSCCON SCIEN SCF STB SRB SSCMOD Description SSC Control Register SSC Interrupt Enable Register SSC Status Register SSC Transmit Buffer Register SSC Receive Buffer Register SSC Mode Test Register Address 93H ACH ABH 94H 95H 96H
The register SSCCON provides the basic control of the SSC functions like general enable/disable, mode selections and transmitter control. Special Function Register SSCCON (Address 93H) MSB 7 SCEN Reset Value : 07H LSB 0 BRS0 SSCCON
Bit No. 93H
6 TEN
5
4
3
2 BRS2
1 BRS1
MSTR CPOL CPHA
Bit SCEN
Function SSC system enable SCEN =0 : SSC subsystem is disabled, related pins are available as general I/O. SCEN=1 : SSC subsystem is enabled. Slave mode - transmitter enable TEN =0 : Transmitter output STO will remain in tristate state, regardless of the state of SLS. TEN = 1 and SLS = 0 : Transmitter will drive the STO output. In master mode the transmitter will be enabled all the time, regardless of the setting of TEN. Master mode selection MSTR=0 : Slave mode is selected MSTR=1 : Master mode is selected This bit has to be set to the correct value depending on the hardware setup of the system before the SSC will be enabled. It must not be modified afterwards. There is no on-chip support for dynamic switching between master and slave mode operation.
TEN
MSTR
Semiconductor Group
6-27
1997-10-01
On-Chip Peripheral Components C540U / C541U
Bit CPOL
Function Clock polarity This bit controls the polarity of the shift clock and in conjunction with the CPHA bit which clock edges are used for sample and shift. CPOL=0 : SCLK idle state is low. CPOL=1 : SCLK idle state is high. Clock phase This bit controls in conjunction with the CPOL bit controls which clock edges are used for sample and shift CPHA=0 : The first clock edge of SCLK is used to sample the data, the second to shift the next bit out at STO. In master mode the transmitter will provide the first data bit on STO immediately after the data was written into the STB register. In slave mode the transmitter (if enabled via TEN) will shift out the first data bit with the falling edge of SLS . CPHA=1 : The first data bit is shifted out with the first clock edge of SCLK and sampled with the second clock edge Baudrate selection bits These bits select one of the possible divide factors for generating the baudrate out of the micrcontroller clock rate fosc . The baudrate is defined by . fosc fosc Baudrate = ------------------------------- = ----------------------------------BRS ( 2 - 0 ) Dividefactor 2*2 for BRS (2-0) 0 BRS(2-0) Divide Factor reserved reserved 8 16 32 64 128 256 Example: Baudrate for fosc = 12 MHz reserved reserved 1.5 MBaud 750 kBaud 375 kBaud 187.5 kBaud 93.75 kBaud 46.875 kBaud
CPHA
BRS2, BRS1, BRS0
0 1 2 3 4 5 6 7 Note:
SSCCON must be programmed only when the SSC is idle. Modifying the contents of SSCCON while a transmission is in progress will corrupt the current transfer and will lead to unpredictable results.
Semiconductor Group
6-28
1997-10-01
On-Chip Peripheral Components C540U / C541U
This register enables or disables interrupt request for the status bits. SCIEN must only be written when the SSC interrupts are disabled in the general interrupt enable register IEN2 (9AH) using bit ESSC otherwise unexpected interrupt requests may occur. Special Function Register SCIEN (Address ACH) MSB 7 - Reset Value : XXXXXX00B LSB 0 SCIEN
Bit No. ACH
6 -
5 -
4 -
3 -
2 -
1
WCEN TCEN
Bit - WCEN
Function Reserved for future use. SSC write collision interrupt enable WCEN =0 : No interrupt request will be generated if the WCOL bit in the status register SCF is set. WCEN=1 : An interrupt is generated if the WCOL bit in the status register SCF is set. SSC transfer completed interrupt enable TCEN =0 : No interrupt request will be generated if the TC bit in the status register SCF is set. TCEN=1 : An interrupt is generated if the TC bit in the status register SCF is set. The SSC interrupt behaviour is in addition affected by bit ESSC in the interrupt enable register IEN2 and by bit 2 in the interrupt priority registers IP0 and IP1.
TCEN
Note:
Semiconductor Group
6-29
1997-10-01
On-Chip Peripheral Components C540U / C541U
Special Function Register SCF (Address ABH) MSB 7 -
Reset Value : XXXXXX00B LSB 0 TC SCF
Bit No. ABH
6 -
5 -
4 -
3 -
2 -
1 WCOL
Bit - WCOL
Function Reserved for future use. SSC write collision detect If WCOL is set it indicates that an attempt was made to write to the shift register STB while a data transfer was in progress and not fully completed. This bit will be set at the trailing edge of the write signal during the erronous write attempt. This bit can be reset in two different ways : 1. writing a "0" to the bit (bit access, byte access or read-modify-write access); 2. by reading the bit or the status register, followed by a write access to STB. If bit WCEN in the SCIEN register is set, an interrupt request will be generated if WCOL is set. SSC transfer completed If TC is set it indicates that the last transfer has been completed. It is set with the last sample clock edge of a reception process. This bit can be reset in two different ways: 1. writing a "0" to the bit (bit access, byte access or read-modify-write access) after the receive buffer register SRB has been read; 2. by reading the bit or the status register, followed by a read access to SRB. If bit TCEN in the SCIEN register is set, an interrupt request will be generated if TC is set.
TC
The register STB (at SFR address 94H) holds the data to be transmitted while SRB (at SFR address 95H) contains the data which was received during the last transfer. A write to the STB places the data directly into the shift register for transmission. Only in master mode this also will initiate the transmission/reception process. When a write collision occurs STB will hold the value written erroneously. This value can be read by reading from STB. A read from the receive buffer register SRB will transfer the data of the last transfer completed. This register must be read before the next transmission completes or the data will be lost. There is no indication for this overrun condition.
Semiconductor Group
6-30
1997-10-01
On-Chip Peripheral Components C540U / C541U
Special Function Register STB (Address 94H) Special Function Register SRB (Address 95H) MSB 7 .7
Reset Value : XXH Reset Value : XXH LSB 0 .0 STB
Bit No. 94H
6 .6
5 .5
4 .4
3 .3
2 .2
1 .1
95H
.7
.6
.5
.4
.3
.2
.1
.0
SRB
After reset the contents of the shift register and the receive buffer register are undefined. The register SSCMOD is used to enable test modes during factory test. It must not be written or modified during normal operation of the C541U. Special Function Register SSCMOD (Address 96H) MSB 7 Reset Value : 00H LSB 0 LSBSM SSCMOD
Bit No. 96H
6
5 0
4 0
3 0
2 0
1 0
LOOPB TRIO
Bit LOOPB
Function SSC loopback enable This bit should be used for test purposes only. LOOPB = 0 : The SSC operates as specified. LOOPB = 1 : The STO output is connected internally via an inverter to the SRI input, allowing to check the transfer locally without a second SSC device. SSC disable tristate mode of SSC inputs This bit should be used for test purposes only. TRIO = 0 : The SSC operates as specified. TRIO = 1 : The SSC inputs will be connected to the output latch of the corresponding port pin. This allows a test of the SSC in slave mode by simulating a transfer via a program setting the port latches accordingly. All bits of this register are set to 0 after reset. When writing SSCMOD, these bits must be written with 0. SSC LSB shift mode If LSBSM is cleared, the SSC will shift out the MSB of the data first LSB last. If LSBSM is set, the SSC will shift out LSB first and MSB last.
TRIO
5-1 LSBSM
Semiconductor Group
6-31
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.4
USB Module
The USB module in the C540U/C541U handles all transactions between the serial USB bus and the internal (parallel) bus of the microcontroller. The USB module includes several units which are required to support data handling with the USB bus : the on-chip USB bus transceiver, the USB memory with two pages of 128 bytes each, the memory management unit (MMU) for USB and CPU memory access control, the UDC device core for USB protocol handling, the microcontroller interface with the USB specific special function registers and the interrupt control logic. A clock generation unit provides the clock signal for the USB module for full speed and low speed USB operation. Figure 6-25 shows the block diagram of the functional units of the USB module with their interfaces.
XTAL1 Pin
XTAL2 Pin
USB D+ Pin
Bus DPin
Osc. 12 MHz
Page 1
7F H
7F H
Transceiver (On-chip) x4 PLL 48 MHz 2 6 MHz Data USB Device Core (UDC) Control
USB Module
Page 0 USB Memory (128 x 8) 00 H
00 H Internal Bus
Data Address MMU USB Memory Management Control
MCU Interface
11 SFR Addr.
Interrupt Generation
MCB03380
Figure 6-25 USB Module Block Diagram
Semiconductor Group
6-32
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.4.1 Transfer Modes USB data transfers take place between host software and a particular endpoint on a USB device. A given USB device may support multiple data transfer endpoints. The USB host treats communications with any endpoint of a USB device independently from any other endpoint. Such associations between the host software and a USB device endpoint are called pipes. As an example, a given USB device could have an endpoint supporting a pipe for transporting data to the USB device and another endpoint supporting a pipe for transporting data from the USB device. The USB architecture comprehends four basic types of data transfers. Table 6-8 USB Transfer Modes Mode Control Function Control data are used to configure devices, data transmission is lossless. Control pipes are bidirectional, data transfer is possible in both directions via one pipe. Endpoint 0 is always configured as control endpoint with a maximum buffer length of 8 bytes. The control endpoint can be configured to handle data packets of 64 bytes maximum length. Isochronous data are continuous and real-time in creation and consumption, such as voice data. In this case, real-time is defined from frame to frame. Isochronous data transfer has the highest priority, but is not always lossless. Isochronous pipes are always unidirectional, so one endpoint can be associated to an IN pipe or an OUT pipe. The C540U/C541U supports up to 64 bytes. Interrupt data are a small amount of data, which are transferred to the host every n frames, with n being programmable by the host. Data delivery is lossless. Interrupt pipes are always unidirectional IN pipes, the maximum data packet length is limited to 64 bytes. Bulk data can be a larger amount of data, which can be split by the host in several data packets witin one frame. Data delivery is lossless. Bulk pipes are always unidirectional, so one endpoint can be associated to an IN pipe or an OUT pipe. The maximum data packet length is limited to 64 bytes.
Isochronous (full speed mode only)
Interrupt
Bulk (full speed mode only)
Semiconductor Group
6-33
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.4.2 USB Memory Buffer Modes 6.4.2.1 Overview
Every endpoint of the USB module in the C540U/C541U can operate in two modes, dual buffer mode and single buffer mode. Each mode provides random or sequential access to the USB memory. Figure 6-26 shows the possible buffer modes.
Buffer Modes
Dual Buffer Mode
Single Buffer Mode
Sequential Access
Random Access
Sequential Access
Random Access
MCD03399
Figure 6-26 Buffer Modes of the C540U/C541U USB Module Single Buffer Mode In single buffer mode, the USB and the CPU use one common USB memory page. The active buffer page is either page 0 or page 1. Dual Buffer Mode In dual buffer mode the USB and the CPU write into different USB memory pages allowing back-toback data transfers. Switching between the pages is done fully automatically, enabling a high data transfer rate between CPU and USB module. Random Access Random access is available in single buffer mode and dual buffer mode. Random access allows to change only a few bytes in a data block of the USB memory buffer. When the CPU has modified the bytes in the data block, setting of bit DONE by software marks the buffer ready for transmission or reception of data over the USB pipe. For modification of a specific byte in the buffer, the CPU must write the address to SFR ADROFF and read/write the data byte from/to register USBVAL. Sequential access In sequential access mode the CPU accesses the data register USBVAL continuously without setting the address of the next USB memory buffer location. This is done automatically if bit INCE (increment enable) in the related SFR EPBCRn is set. After a specific number of CPU accesses (as defined in SFR EPLENn), the buffer has been read/written by the CPU and is empty/full. Setting of bit DONE by software, manually or automatically, marks the USB buffer ready. Note : Only buffers for device to host pipes can be written.
Semiconductor Group
6-34
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.4.2.2
Single Buffer Mode
In single buffer mode the USB and the CPU share one common USB memory page. The active buffer page can be either page 0 or page 1. Back-to-back transfers are not possible in this mode. Easy data storage and controlling can be achieved in this mode. E.g. a once created data set for an interrupt endpoint can be stored permanently in USB memory. As a result, an additional memory space for data storage is no longer needed. 6.4.2.2.1 USB Write Access Figure 6-27 shows the basic flowchart of a USB write access to one USB memory buffer in single buffer mode.
Buffer is empty: USB write Access Enabled CPU read Access Disabled
USB write Request? YES Buffer is written by USB
NO
EOD = 1
Buffer full? YES Buffer is full: USB write Access Disabled CPU read Access Enabled
NO
SOD = 1
Buffer can be read by CPU
YES
Buffer empty?
NO
MCD03400
Figure 6-27 USB Write Access in Single Buffer Mode - Buffer Handling Semiconductor Group 6-35 1997-10-01
On-Chip Peripheral Components C540U / C541U
Figure 6-28 shows more details of an USB write access to USB memory in single buffer mode. After SOF(n) (start of frame) occured at 1 , the USB starts writing at 2 a fixed number of bytes into the USB memory. A byte counter is incremented after every USB memory write operation. When the USB memory write operation (Len(n)) is finished correctly, bit SOD (start of data) is set at 3 , indicating a full USB memory buffer. Furthermore, the byte counter value is stored in the corresponding length register, indicating the number of bytes which have been transferred and can be now read by the CPU. Subsequently, the CPU can read data bytes from USB memory, generating an EOD (end of data) at 4 after the last byte has been read. Bit EOD set indicates an empty USB buffer, which now can be written again by the USB. Figure 6-28 also shows a second USB write access operation with a different number of bytes (Len(n+1)), where the CPU read operation from the USB memory is interrupted twice.
Number of Data Bytes in USB Buffer
SOD Set SOD Set
3 3
Len (n) Len (n+1)
4
4
EOD Set
1 2 1 2
EOD Set
Time Frame n+1 SOF (n+2) Set
Frame n SOF (n) Set USB write Accesses CPU read Accesses
MCT03401
Figure 6-28 Single Buffer Mode : Standard USB Write Access
Note: The CPU accesses shown in the following diagrams assume that bit INCE in the corresponding endpoint control register is set. A frame is the 1 ms time interval defined by the USB host. Every frame begins with a SOF token (start-of-frame).
Semiconductor Group
6-36
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.4.2.2.2 USB Read Access Figure 6-29 shows the basic flowchart of a USB read access from one USB memory buffer in single buffer mode.
Buffer is empty: USB read Access Disabled CPU write Access Enabled
Buffer can be written by CPU
Buffer full? YES SOD = 1 Buffer is full: USB read Access Enabled CPU write Access Disabled
NO
EOD = 1
USB read Request? YES Buffer is read by USB
NO
YES
Buffer empty?
NO
MCD03402
Figure 6-29 USB Read Access in Single Buffer Mode - Buffer Handling
Semiconductor Group
6-37
1997-10-01
On-Chip Peripheral Components C540U / C541U
The standard USB read access as shown in figure 6-30 supports random and sequential CPU access mode of the USB memory. The memory buffer full condition is true when a predefined number of bytes (MaxLen) has been written by the CPU or when bit DONE has been set by software. After SOF(n) occured at 1 with a full USB memory buffer, the USB reads the buffer. Bit SOD is set at the end of the USB buffer read operation at 2 , indicating an empty USB memory buffer. Now, the CPU can write again data into the USB memory buffer until a determined number (MaxLen) of bytes are transfered or until bit DONE has been set by software. The MaxLen value must be previously set by software. When the actual USB memory buffer address offset is equal to MaxLen, bit EOD is set at 3 to indicate a full buffer. The USB memory buffer address offset is automatically incremented with every CPU write access to USB memory buffer if bit INCE is set. During the next frame (after SOF(n+1)) is set at 4 ) the USB memory buffer can be read by the USB. Bit SOD is set again when the USB memory buffer becomes empty again. If bit DONE is set by the CPU (at 5 ), the buffer is declared by the CPU to be full, even if the address offset does not reach the value of MaxLen.
Number of Data Bytes in USB Buffer
EOD Set
MaxLen
3
2
DONE Set SOD Set
4 5
SOD Set
1
Time Frame n SOF (n) Set USB read Accesses SOF (n+1) Set CPU write Accesses Frame n+1 SOF (n+2) Set
MCT03403
Figure 6-30 Single Buffer Mode : Standard USB Read Access
Semiconductor Group
6-38
1997-10-01
On-Chip Peripheral Components C540U / C541U
The start-of-frame-done enable feature (SOFDE=1) is useful for USB memory read accesses when the number of data bytes to be transferred from CPU to USB is not predictable (see figure 6-31). The CPU can write data as desired to USB memory until a SOF occures (every 1 ms). The automatic setting of bit SOF causes bit EOD to be set (at 1 ). This indicates the CPU that no CPU action on this buffer is required until a USB read operation has been finished (bit SOD set at 2 ). Setting of SOD indicates an empty USB memory to the CPU which can start again writing data into USB memory.
Number of Data Bytes in USB Buffer
MaxLen
1 2
SOD Set
SOD Set
Time Frame n SOF (n) and EOD Set USB read Accesses CPU write Accesses SOF (n+1) and EOD Set
MCT03404
Frame n+1
Figure 6-31 Single Buffer Mode : USB Read Access with Start-of-Frame-Done Enabled
Semiconductor Group
6-39
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.4.2.3
Dual Buffer Mode
In dual buffer mode, both USB memory pages (page 0 and page 1) are used for data transfers. The logical assignment of the memory pages to CPU or USB is automatically switched. The following two figures show the buffer handling concept in dual buffer mode for the USB read access and USB write access.
CPU Buffer Handling
USB Buffer Handling
CPU Page is empty : CBF = 0 CPU write Access Enabled
USB Page is full : UBF = 1 USB read Access Enabled
CPU writes 1 Byte
USB read Request? YES USB reads Buffer
NO
NO
CPU Buffer full? YES
SOD = 1
CPU Buffer is full : CBF = 1 CPU write Access Disabled
USB Buffer is empty: UBF = 0 USB read Access Disabled
EOD = 1
NO
USB Page empty? YES
CPU Page full? YES
NO
Pages are swapped (CBF = 1 and UBF = 0)
MCB03405
Figure 6-32 USB Read Access in Dual Buffer Mode - Buffer Handling
Semiconductor Group
6-40
1997-10-01
On-Chip Peripheral Components C540U / C541U
CPU Buffer Handling
USB Buffer Handling
CPU Page is full : CBF = 1 CPU read Access Enabled
USB Page is empty : UBF = 0 USB write Access Enabled
CPU reads 1 Byte
USB write Request? YES USB writes Buffer
NO
NO
CPU Buffer empty? YES
SOD = 1
CPU Buffer is empty : CBF = 0 CPU read Access Disabled
USB Buffer is full: UBF = 1 USB write Access Disabled
EOD = 1
NO
USB Page full? YES
CPU Page empty? YES
NO
Pages are swapped (CBF = 0 and UBF =1)
MCB03406
Figure 6-33 USB Write Access in Dual Buffer Mode - Buffer Handling
Semiconductor Group
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1997-10-01
On-Chip Peripheral Components C540U / C541U
Figure 6-34 describes an example of a USB read operation in sequential mode with both buffers empty at the beginning of the USB read operation. The CPU starts writing data with sequential access (INCE=1) to the buffer assigned to the CPU at 1 . By definition, the buffer is full when MaxLen is reached at 2 . The second buffer assigned to the USB is empty (UBF=0) and as a result both buffers are logically swapped. Now the buffer assigned to USB is full (UBF=1) and an USB read access can take place. After the USB read access, the buffer assigned to the USB is empty again with UBF=0. During the USB read access the CPU is still allowed to write into its assigned buffer. When reaching MaxLen at 3 , the CPU buffer is full and both buffers are again logically swapped. The USB further execute its read access.
Number of Data Bytes
3
MaxLen CPU Buffer Page 0
2
Page 1
Page 1
CBF =0
1
Time Swap Buffer UBF = 1 Page 1 Page 0 Swap Buffer UBF = 1 Page 1
MaxLen USB Buffer UBF =0
UBF = 0 Frame n Frame n+1 SOF (n+1) Set CPU write Accesses SOF (n+2) Set
Time
SOF (n) Set USB read Accesses
MCT03407
Figure 6-34 Dual Buffer Mode USB Read Access : Buffer Switching when MaxLen is reached In dual buffer mode, the physical assignment of the USB memory pages (page 0 or page 1) to either CPU buffer or USB buffer is controlled automatically in the USB module and cannot be selected by software.
Semiconductor Group
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On-Chip Peripheral Components C540U / C541U
Another way to initiate buffer switching is setting bit DONE by software. This feature, which is shown in figure 6-35 for USB read access, can be used to transfer a variable number of bytes. The maximum number of bytes to be transferred is still determined by MaxLen, which is not changed when bit DONE is set. The actual packet length (Len1 or Len2) is the number of bytes which have been written to the buffer before bit DONE is set.
Number of Data Bytes DONE = 1 MaxLen Len1 Len2 CPU Buffer DONE = 1
2 3
Page 0 CBF =0
1
Page 1
Page 1 Time
Swap Buffer
Swap Buffer UBF = 1
MaxLen Len1 Len2 USB Buffer UBF = 1 Page 1 Page 0
Page 1
UBF =0 Frame n SOF (n) Set USB read Accesses SOF (n+1) Set CPU write Accesses
UBF = 0 Frame n+1 SOF (n+2) Set
Time
MCT03408
Figure 6-35 Dual Buffer Mode USB Read Access : Buffer Switching by Setting Bit DONE
Semiconductor Group
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1997-10-01
On-Chip Peripheral Components C540U / C541U
If bit SOFDE is set, buffer switching is done automatically after SOF (start of frame) has been detected by the USB. Figure 6-36 describes this functionality for USB read access for this case. The buffer which contains the latest data from the CPU is tagged valid for USB access (UBF=1) at 1 and the buffers are swapped if the USB buffer is empty. After the USB read access has occured at 2 , this buffer assigned to USB is empty again (UBF=0) and can be swapped again as soon as the CPU has filled its buffer (at 3 ). The number of bytes in the buffer is less or equal MaxLen. The MaxLen threshold is always active, but an occurrence of SOF (if SOFDE=1) or setting bit DONE by software are used to tag the CPU buffer full before reaching MaxLen.
Number of Data Bytes
MaxLen Len1 Len2 CPU Buffer
1 3
Page 0
Page 1
CBF =0 Swap Buffer MaxLen Len1 Len2 USB Buffer Page 1 Page 0 Swap Buffer
Time
UBF =0 Frame n SOF (n) Set USB read Accesses SOF (n+1) Set
2
UBF = 0 Time Frame n+1 SOF (n+2) Set
MCT03409
CPU write Accesses
Figure 6-36 Dual Buffer Mode USB Read Access: Buffer Switching on SOF with SOFDE=1
Semiconductor Group
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1997-10-01
On-Chip Peripheral Components C540U / C541U
If the number of data bytes to be transferred is greater than the maximum packet size (given by MaxLen), the data is split up automatically into packets, which are transferred one after the other. Figure 6-37 gives an example of an USB read access, where data from the CPU is split up into two packets. When MaxLen is reached during the CPU write access, the currently active buffer is switched to USB side (UBF=1). The CPU continues writing data to the buffer. When the complete data packet has been written to the buffer by the CPU, bit DONE is set by software to indicate the end of the data packet (CBF=1). In the example, the USB buffer has not been read out. It is still full for the USB and can not be swapped (CBF=UBF=1). When the USB read access has occured (CBF=0), the buffers are automatically swapped and bit SOD is set.
Number of Data Bytes
MaxLen CPU Buffer Page 1 Page 0 DONE = 1 CBF = 1 SOD = 1 Time
1
Page 1
CBF =0 Swap Buffer Page 0 UBF = 1 Swap Buffer
EOD = 1 Page 1
MaxLen USB Buffer
Page 0 UBF = 1
UBF =0 Frame n SOF (n) Set USB read Accesses SOF (n+1) Set CPU write Accesses Frame n+1 SOF (n+2) Set
Time
MCT03410
Figure 6-37 Double Buffer Mode USB Read Access: Data Length greater than Packet Length (MaxLen)
Semiconductor Group
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On-Chip Peripheral Components C540U / C541U
In general, three criteria for buffer switching are implemented in the USB module : a) For sequential access, the address offset register ADROFF is automatically incremented after each read or write action of the CPU. The address offset value (before incrementing) represents the number of bytes stored in USB memory for a specific endpoint. If the address offset value (after incrementing) reaches the value stored in endpoint length register EPLENn, the currently active buffer is tagged full (USB read access - all bytes have been written by CPU, CBF=1) or empty (USB write access - all bytes have been read by CPU, CBF=0). b) When Bit DONE, which is located in the endpoint buffer status register EPBSn, is set, software buffer switching is initiated. This action is independent from the number of bytes which have been handled by the CPU (possible in sequential access mode (INCE=1) and random access mode (INCE=0)). On CPU read accesses, the buffer is declared empty and bit CBF is cleared. If the buffer assigned to the USB is full (UBF=1), the buffers are immediately swapped. In this case, register EPLENn contains the number of received bytes. On CPU write accesses, two different cases must be distinguished. For random accesses, the number of bytes of one packet is fixed by the value in register EPLENn and does not change. For sequential accesses, the number of written bytes represents the packet size. In this case, the actual value of register ADROFF is transferred to register EPLENn when bit DONE is set. c) The third criteria for buffer switching is the automatic buffer switching on detection of SOF (see figure 6-37). This feature can be individually enabled (SOFDE=1) or disabled (SOFDE=0) by software selectively for each endpoint.
Semiconductor Group
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1997-10-01
On-Chip Peripheral Components C540U / C541U
6.4.3 USB Memory Buffer Organization The address generation of the USB memory buffer is based on address offset and base address pointer. This scheme allows flexible and application specific buffer allocation and management. The length of an endpoint buffer can be up to 8, 16, 32, or 64 bytes. The start address of each endpoint buffer can be located to memory locations according table 6-9. Table 6-9 USB Buffer Length and Base Addresses Values Buffer Length 8 bytes 16 bytes 32 bytes 64 bytes Valid Buffer Base Addresses 08H, 10H, 18H, 20H, 28H, 30H, 38H, 40H, 48H, 50H, 58H, 60H, 68H, 70H, 78H 10H, 20H, 30H, 40H, 50H, 60H, 70H 20H, 40H, 60H 40H
In order to avoid unused memory space between two endpoint buffers, the largest buffer should be located at the highest address. This structure should be used to allocate USB memory for all endpoint buffers. The base address for the setup packet is always located at address 00H. This leads to a typical USB buffer structure as shown in figure 6-38 with a buffer length of 64 bytes for endpoint 2, 16 bytes for endpoints 1 and 3, 8 bytes for endpoint 0, and a predefined length of 8 bytes for endpoint 0 and the setup token.
7FH
Endpoint 2 Buffer Buffer Block 40H Endpoint 3 Buffer Endpoint 1 Buffer Endpoint 0 Buffer 30H 20H 18H Endpoint 2 Endpoint 3 Endpoint 1 Endpoint 0 Setup Token EPBAn EPLENn
EPBA2=08H EPLEN2=40H EPBA3=06H EPLEN3=10H EPBA1=04H EPLEN1=10H EPBA0=03H EPLEN0=08H Adress 00H 8 Bytes on page 0
Setup Token
00H
Figure 6-38 Endpoint Buffer Allocation (Example: 4 Endpoints) Semiconductor Group 6-47 1997-10-01
On-Chip Peripheral Components C540U / C541U
6.4.4 USB Memory Buffer Address Generation The generation of an USB memory address for USB access (read or write) depends on the EPNum (endpoint number) information, which has been transmitted to the USB module during the software initialization procedure. This EPNum information is used for the selection of an endpoint specific base address register. As the maximum data packet length of each endpoint can individually be programmed, there are some fixed start addresses for the endpoints. The user program defines the base address for the first data byte of the corresponding endpoint by writing the endpoint specific base address register EPBAn. The length depends on the amount of data to be read or written. The user must take care to assign a buffer space at least as large as the maximum packet size of the endpoint. The address of the currently accessed byte in the USB memory area of the selected endpoint is defined by an address offset, which must be added to the endpoint base address in order to get the correct address for the USB memory buffer. The structure is shown in figure 6-39.
EPBA 0 PAGE 0 EPBA 1 PAGE 1 EPBA 2 PAGE 2 EPBA 3 PAGE 3 EPBA 4 PAGE 4
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
A06 A05 A04 A03 A16 A15 A14 A13 A26 A25 A24 A23 A36 A35 A34 A33 A46 A45 A44 A43 An6 - An3 EPBAn + ADROFF 0 0 0 An6 An5 An4 An3 0 PAGEn 0 0 0 USB Memory Page 1 Page 0 MUX EPNum of the Actual Endpoint
AO5 AO4 AO3 AO2 AO1 AO0
= USB Memory Addr.
AD6 AD5 AD4 AD3 AD2 AD1 AD0
Note: Only one Bit of the Bit pairs An5/AO5, An4/AO4, An3/AO3 can be set at a time.
MCD03411
Figure 6-39 USB Memory Address Generation With the software initialization of the USB modul as described in section 6.4.5, each endpoint is initialized with the EPNum value which is used at the USB memory address generation to select the actual endpoint base address register. Further, in single buffer mode the bit PAGEn is used to select one of the USB memory pages In dual buffer mode bit PAGEn has no effect.
Semiconductor Group
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On-Chip Peripheral Components C540U / C541U
6.4.5
Initialization of USB Module
After a hardware reset operation bits PCLK, SPEED, and UCLK are set to 0. Depending on the required operating mode of the USB module a well defined procedure must be executed for switching on the clock for the USB module : - Full speed mode USB PLL is switched on by setting bit PCLK waiting 3 ms for PLL being locked setting bit UCLK setting bit UCLK only
- Low speed mode
This switch-on procedure after a hardware reset assures a proper operation of the USB clock system. When the USB clock system is switched on, a software initialization procedure must follow This procedure must execute the following steps : - Setting bit SWR in register DCR starts the software reset operation for the complete USB module. For a full speed device, bit SPEED must be set together with SWR in the same instruction (write protection of SPEED bit). - When the software reset is finished, bit SWR is cleared by hardware and bit DINIT is set to indicate the start of the initialization sequence. - The USB module must be functionally initialized from the CPU by writing five configuration bytes for each endpoint to the USBVAL register. Thereafter, bit DONE0 in register EPBS0 must be set by software. Figure 6-40 shows the 5-byte configuration block which must be transmitted by the CPU to the USB module via the USBVAL register for each endpoint. The gray shaded fields have a fixed "0" or "1" value for each endpoint while the white bitfields have to be filled by parameters according table 610.
Byte 0 Byte 1 Byte 2 Byte 3 Byte 4
0 0 0
EPNum EPType EPPackSize
0 EPDir
1 msb
0
0
EPPackSize lsb 0
0 0
0 0
0 0
0 0
0 0 0
EPNum 0 0
Constant data for each USB configuration block Figure 6-40 USB Configuration Block The five byte USB configuration block must be transfered sequentially (byte 0 to byte 4) from the CPU to the USB module for each endpoint beginning with endpoint 0, followed by the USB configuration block for endpoint 1 and so on up to the USB configuration block for endpoint 4.
Semiconductor Group
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1997-10-01
On-Chip Peripheral Components C540U / C541U
EPNum is set to 000B, 001B, .... up to 100B for endpoints 0 up to 4. After this action, bit DINIT is reset by hardware and the software reset and initialization sequence are finished. Table 6-10 Bitfield Definition of USB Configuration Block Bitfield EPNum Description This 3-bit field specifies the number of the endpoint (0-4) for which the actual configuration byte block is valid. This 3-bit field must be referenced in byte 0 and byte 3 of a configuration byte block. This 2-bit field defines the type of the endpoint 00 : Control endpoint 01 : Isochronous endpoint 10 : Bulk endpoint 11 : Interrupt endpoint Endpoint 0 must be setup for control endpointThis bit defines the direction of the endpoint 0 : In (packets to be transferred from CPU to Host) 1 : Outr (packets to be transferred from Host to CPU) This 10-bit field defines the maximum packet size to be transferred to this endpoint within the range from zero up to 1023 bytes. The configuration of EPPackSize has to be in harmony to the USB specification.
EPType
EPDir
EPPackSize
Semiconductor Group
6-50
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.4.6 Control Transfer A control transfer consists of at least two and perhaps three stages. This chapter gives a short description of these stages of a control transfer and the associated configuration of the control and status bits. 6.4.6.1 Setup Stage
Control transfer always begin with a setup stage that transfers information to a target device, defining the type of request being made to the USB device. The standard commands except the "set_descriptor" and "get_descriptor" command are handled by the USB module automatically without CPU interaction. If the command is not handled by the USB module automatically, a setup interrupt (bit SUI is set) indicates the end of a setup phase. Additionally, the status and control bits UBF, CBF and SOD are reset. 6.4.6.2 Data Stage
This stage is defined only for requests that require data tranfers. The direction of this data stage is always predicted to be from Host to Device (bit DIR is automatically cleared after the setup stage occured). The first data packet may immediately be send from the Host to the control endpoint according to this configuration of bit DIR, while NACK will be automatically returned from the Device to the Host in case of USB read access. The configuration of bit DIR=0 predicts an USB write access, while an USB read access causes automatically a NACK (no acknowledge) to be generated and the direction bit to be changed (DIR=1, USB read access). The direction of the next transfer can also be predicted under software control (bit SETWR is set) to be an USB read access (DIR=1). This feature is used, if the direction of the data stage is known and the data packet to be transferred from the CPU to the Host is set up before the next USB access occured. Therefore, the direction bit must be changed under software control, to be able to transfer the data packet within the first USB read access. Status bit SOD is set under hardware control to indicate valid data to be read by CPU in case of USB write access, or data to be written by CPU in case of USB read access. 6.4.6.3 Status Stage
The status stage is always performed to report the result of the requested operation. A status stage initiated by the Host, but not terminated according to the configuration of ESP (ESP=0) is indicated by a status interrupt (bit STI is set). Bit ESP has to be set under software control to enable the acknowledge of the status stage.
Semiconductor Group
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On-Chip Peripheral Components C540U / C541U
6.4.7 Register Set Two different kinds of registers are implemented in the USB module. The global registers (GEPIR, EPSEL, ADROFF, USBVAL) describe the basic functionality of the complete USB module and can be accessed via unique SFR addresses. For reduction of the number of SFR addresses which are needed to control the USB module inside the C540U/C541U, device registers and endpoint registers are mapped into an SFR address block of seven SFR addresses (C1H to C7H). The endpoint specific functionality of the USB module is controlled via the device registers DCR, DPWDR, DIER, DIRR and the frame number registers. An endpoint register set is available for each endpoint (n=0..4) and describes the functionality of the selected endpoint. Figure 6-41 explains the structure of the USB module registers.
Global Registers GEPIR (D6 H ) 0 0 0 .4 .3 .2 .1 .0 ADROFF (D4 H ) 0 0 .5 .4 .3 .2 .1 .0
USBVAL (D3 H ) EPSEL (D2 H )
.7 .6 .5 .4 .3 .2 .1 .0
.7 0 0 0 0 .2 .1 .0 Decoder
Device Registers C1 H C3 H C4 H C6 H C7 H DCR
Endpoint 0 Registers C1 H EPBC0 C2 H EPBS0 C3 H C4 H EPIE0 EPIR0
Endpoint 1 Registers C1 H EPBC1 C2 H EPBS1 C3 H C4 H EPIE1 EPIR1
Endpoint 2 Registers C1 H EPBC2 C2 H EPBS2 C3 H C4 H EPIE2 EPIR2
Endpoint 3 Registers C1 H EPBC3 C2 H EPBS3 C3 H C4 H EPIE3 EPIR3
Endpoint 4 Registers C1 H EPBC4 C2 H EPBS4 C3 H C4 H EPIE4 EPIR4
C2 H DPWDR DIER DIRR
C5 H reserved FNRL FNRH
C5 H EPBA0 C6 H EPLEN0 C7 H reserved
C5 H EPBA1 C6 H EPLEN1 C7 H reserved
C5 H EPBA2 C6 H EPLEN2 C7 H reserved
C5 H EPBA3 C6 H EPLEN3 C7 H reserved
C5 H EPBA4 C6 H EPLEN4 C7 H reserved
MCD03312
Figure 6-41 Register Structure of the USB Module
Note: In the description of the USB module registers bits are marked as "rw", "r", or "w". Bits marked as "rw" can be read and written. Bits marked as "r" can be read only. Writing any value to "r" bits has no effect. Bits marked as "w" are used to execute internal commands which are triggered by writing a 1. Writing a 0 to "w" bits has no effect. Reading "w" bits returns a 0.
Semiconductor Group
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6.4.7.1
Global Registers
The global registers GEPIR, EPSEL, ADROFF, and USBVAL describe the global functionality of the USB module and can be accessed via unique SFR addresses. The Endpoint Select Register EPSEL contains 4 bits which are used to select one of the register blocks of the five endpoint register blocks or the device register block. These register blocks are mapped to the same SFR address range of C1H to C7H. USB Endpoint Select Register EPSEL (Address D2H) Bit No. D2H MSB 7 EPS7 rw Bit EPS7 EPS2 EPS1 EPS0 Reset Value : 80H LSB 0 EPS0 rw EPSEL
6 0 r
5 0 r
4 0 r
3 0 r
2 EPS2 rw
1 EPS1 rw
Function Endoint / device register block select bits These four bits select the active register block of endpoint or device registers. EPS7 1 0 0 0 0 0 0 0 EPS2 X 0 0 0 0 1 1 1 EPS1 X 0 0 1 1 0 0 1 EPS0 X 0 1 0 1 0 1 X Selected Register Device register set selected Endpoint 0 register set selected Endpoint 1 register set selected Endpoint 2 register set selected Endpoint 3 register set selected Endpoint 4 register set selected reserved reserved
Table 6-11 shows the register definitions of each endpoint or device register block in detail.
Semiconductor Group
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On-Chip Peripheral Components C540U / C541U
Table 6-11 Endpoint/Device Register Set Address Assignment EPSEL 1XXXXXXXB SFR Addr. C1H C2H C3H C4H C5H C6H C7H C1H C2H C3H C4H C5H C6H C7H Selected Register DCR : Device Control Register DPWDR: Device Power Down Register DIER : Device Interrupt Enable Register DIRR : Device Interrupt Request Register reserved address FNRL : Frame Number Register (low byte) FNRH : Frame Number Register (high byte) EPBCn : EPBSn : EPIEn : EPIRn : EPBAn : EPLENn: Endpoint n Buffer Control Register Endpoint n Buffer Status Register Endpoint n Interrupt Enable Register Endpoint n Interrupt Request Register Endpoint n Base Address Register Endpoint n Buffer Length Register reserved address (n=0-4) (n=0-4) (n=0-4) (n=0-4) (n=0-4) (n=0-4)
(Device register block selected)
0XXXXnnnB (nnn = 000B to 100B) (Endpoint nnnB register block selected)
The data transfers between USB memory and the CPU are handled via the SFR USBVAL. With a CPU write access to USBVAL, the value written into it is transferred to the USB memory location which is defined by the content of the endpoint specific endpoint base address register EPBAn and the content of the address offset register ADROFF. At USB memory read accesses from the CPU the data is transfered in reverse direction. A write operation to USBVAL is only successfull if either DIR=0 and CBF=1 (write operation) or DIR=1 and CBF=0 (read operation). USB Data Register USBVAL (Address D3H) Bit No. D3H MSB 7 .7 rw Bit USBVAL.7-0 6 .6 rw Function USB data value USBVAL stores the 8-bit data byte during transfers from CPU to USB memory and from USB memory to CPU. Bit NOD in the EPIRn register indicates when the CPU processes an USBVAL read operation with an empty USB buffer or a USBVAL write operation to a full USB buffer. 5 .5 rw 4 .4 rw 3 .3 rw 2 .2 rw 1 .1 rw Reset Value : 00H LSB 0 .0 rw USBVAL
Semiconductor Group
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On-Chip Peripheral Components C540U / C541U
In most cases the CPU accesses only one endpoint buffer until it is full (CBF=1 at CPU write access) or empty (CBF=0 at CPU read access). As the USB memory size is 128 bytes per page, the maximum packet length is limited to 64 bytes. Therefore, only the lowest 6 bits of ADROFF (AO5..AO0) are required for offset definiton. A write operation to ADROFF is only successfull if either DIR=0 and CBF=1 (write operation) or DIR=1 and CBF=0 (read operation). USB Address Offset Register ADROFF (Address D4H) Bit No. D4H MSB 7 0 r Bit AO5-0 Reset Value : 00H LSB 0 AO0 rw ADROFF
6 0 r
5 AO5 rw
4 AO4 rw
3 AO3 rw
2 AO2 rw
1 AO1 rw
Function USB address offset register AO5-0 stores the 6-bit offset address for USB memory buffer addressing by the CPU.
After each modification (automatical or by write action) of the address offset register ADROFF, the value pointed to is automatically read out of USB memory and transferred to register USBVAL.
Semiconductor Group
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On-Chip Peripheral Components C540U / C541U
The global endpoint interrupt request register GEPIRn (n=0-4) contains one flag for each endpoint which indicates whether one or more of the eight endpoint specific interrupt requests have become active. If a request flag in GEPIR is set, it is automatically cleared after a read operation of the corresponding endpoint specific EPIRn register. USB Global Endpoint Interrupt Request Register GEPIR (Address D6H) Bit No. D6H MSB 7 0 r Bit EPI4 EPI3 EPI2 EPI1 EPI0 6 0 r Function Endpoint 4 interrupt request flag If EPI4 is set, an endpoint 4 interrupt request is pending. Endpoint 3 interrupt request flag If EPI3 is set, an endpoint 3 interrupt request is pending. Endpoint 2 interrupt request flag If EPI2 is set, an endpoint 2 interrupt request is pending. Endpoint 1 interrupt request flag If EPI1 is set, an endpoint 1 interrupt request is pending. Endpoint 0 interrupt request flag If EPI0 is set, an endpoint 0 interrupt request is pending. 5 0 r 4 EPI4 r 3 EPI3 r 2 EPI2 r 1 EPI1 r Reset Value : 00H LSB 0 EPI0 r GEPIR
Bit 4 (GEPIEn) of the specific endpoint buffer control register EPBCn must be set if EPIn should generate an interrupt. Additionally, bit EA (IEN0.7) and bit EUEI (IEN1.1) must be set when an endpoint interrupt should be triggered.
Semiconductor Group
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On-Chip Peripheral Components C540U / C541U
6.4.7.2
Device Registers
The device registers can only be accessed when global register EPSEL(D2H) = 80H. The following SFRs are defined as device register : - - - - - - DCR PDWDR DIER DIRR FNRL FNRH Device Control Register Device Power Down Register Device Interrupt Enable Register Device Interrupt Request Register Frame Number Register (low byte) Frame Number Register (high byte)
The device control register includes control and status bits which indicate the current status of the USB module and the status of the USB bus. USB Device Control Register DCR (Address C1H) Bit No. C1H MSB 7 SPEED rw Bit SPEED 6 DA r 5 SWR rw 4 SUSP r 3 DINIT r 2 RSM rw Reset Value : 000X0000B 1 UCLK rw LSB 0 PCLK rw DCR
Function Low / full speed select Bit SPEED configures the USB module in the C540U/C541U for full speed (12 MBaud) or low speed (1.5 MBaud) mode. This bit can only be written with bit SWR=1 (software reset). After hardware reset the USB module runs in low speed mode and the PLLx4 is automatically disabled. If SPEED=0, low speed mode selected (default after reset) If SPEED=1, full speed mode selected. Device attached Bit DA reflects the state of pin DADD, which can be used to indicate whether the device is attached to the USB bus or not in self-powered mode. If pin DADD is 0, bit DA=0. If pin DADD is 1, bit DA=1. Software reset Setting bit SWR initiates a software reset operation of the USB device. This bit is cleared by hardware after successful reset operation. SWR can not be reset by software. Suspend mode This bit is set when the USB is idle for more than 3 ms. It will remain set until there is a non idle state on the USB cable or when bit RSM is set.
DA
SWR
SUSP
Semiconductor Group
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Bit DINIT
Function Device initialization in progress At the end of a software reset, bit DINIT is set by hardware. After software reset of the USB module, the USB module must be initialized by the CPU. When DINIT is set after a software reset, 5 bytes for each endpoint must be written to SFR USBVAL. After the 25th byte, bit DONE0 has to be set by software. Bit DINIT is reset by software after a successful initialization sequence. Resume bus activity When the USB device is in suspend mode, setting bit RSM resumes bus activity of the device. In response to this action, the USB will disassert the suspend bit and will perform the remote wake-up operation. Writing 0 to RSM has no effect, the bit is reset if bit SUSP is 0. UDC clock selection Bit UCLK controls the functionality of the USB core clock in full speed mode (SPEED=1) as well as in low speed mode (SPEED=0).. If UCLK=0, the USB core clock (48 MHz or 6 MHz) is disabled. If UCLK=1, the USB core clock (48 MHz or 6 MHz) is enabled. PLL clock select Bit PCLK controls the 48 MHz PLL. If PCLK=0, the 48 MHz PLL is disabled (default after reset). If PLCK=1, the 48 MHz PLL is enabled. For power consumption and EMI reasons, the 48 MHz PLL should be disabled in low speed mode (SPEED=0).
RSM
UCLK
PCLK
Semiconductor Group
6-58
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On-Chip Peripheral Components C540U / C541U
The device power down register DPWDR includes two bits which allow to switch off the USB transmitter and receiver circuitry selectively for power down mode operation. USB Device Power Down Register DPWDR (Address C2H) Bit No. C2H MSB 7 0 r Bit TPWD 6 0 r Function USB Transmitter Power Down Setting bit TPWD puts the USB transmitter into power down mode. After a wakeup from software power down mode operation, bit TPWD must be cleared by software to enable again data transmission. If TPWD=0, the transmitter is active (default after reset). If TPWD=1, the transmitter is in power down mode. USB Receiver Power Down Setting bit RPWD puts the USB receiver into power down mode. After a wake-up from software power down mode operation, bit RPWD must be cleared by software to enable again data reception. If RPWD is set, the USB bus cannot wake-up the C540U/C541U form power down mode. If RPWD=0, the USB receiver is active (default after reset). If RPWD=1, the USB receiver is in power down mode. 5 0 r 4 0 r 3 0 r 2 0 r 1 TPWD rw Reset Value : 00H LSB 0 RPWD rw DPWDR
RPWD
Semiconductor Group
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1997-10-01
On-Chip Peripheral Components C540U / C541U
The device interrupt enable register DIER contains the enable bits for the different types of device interrupts. With these bits, the device interrupts can be individually enabled or disabled. The general device interrupt enable bit EUDI is located in SFR IEN1. A device interrupt can be only generated if EUDI and EA (global interrupt enable bit in IEN0) are set too. USB Device Interrupt Enable Register DIER (Address C3H) Bit No. C3H MSB 7 SE0IE rw Bit SE0IE 6 DAIE rw 5 DDIE rw 4 SBIE rw 3 SEIE rw 2 STIE rw 1 SUIE rw Reset Value : 00H LSB 0 SOFIE rw DIER
Function Single ended zero Interrupt Enable Setting bit SE0IE enables the generation of a device interrupt each time a single ended zero is detected for more than 2.5s (reset by host, not EOP). If SE0IE=0, the single ended zero interrupt is disabled. If SE0IE=1, the single ended zero interrupt is enabled. Device attached interrupt enable Setting bit DAIE enables the generation of a device interrupt when it is attached to the USB bus. If DAIE=0, the device attached interrupt is disabled. If DAIE=1, the device attached interrupt is enabled. Device detached interrupt enable Setting bit DDIE enables the generation of a device interrupt when it is detached from the USB bus. If DDIE=0, the device detached interrupt is disabled. If DDIE=1, the device detached interrupt is enabled. Suspend begin interrupt enable Setting bit SBIE enables the generation of a device interrupt if bit SBI is set, this means the suspend mode is entered. If SBIE=0, the suspend begin interrupt is disabled. If SBIE=1, the suspend begin interrupt is enabled. Suspend change interrupt enable Setting bit SEIE enables the generation of a device interrupt if bit SEI is set, this means the suspend mode is left. If SEIE=0, the suspend change interrupt is disabled. If SEIE=1, the suspend change interrupt is enabled. Status interrupt enable Bit STIE enables the generation of a device interrupt at the end of the status phase of a control transfer. If STIE=0, the status interrupt is disabled. If STIE=1, the status interrupt is enabled.
DAIE
DDIE
SBIE
SEIE
STIE
Semiconductor Group
6-60
1997-10-01
On-Chip Peripheral Components C540U / C541U
Bit SUIE
Function Setup interrupt enable Bit SUIE enables the generation of a device interrupt on a succesful reception of a setup packet which must be processed by the CPU. If SUIE=0, the setup interrupt is disabled. If SUIE=1, the setup interrupt is enabled. Start of frame interrupt enable bit SOFIE enables the generation of a device interrupt on the detection of a start of frame packet on the USB. If SOFIE=0, the start of frame interrupt is disabled. If SOFIE=1, the start of frame interrupt is enabled.
SOFIE
Semiconductor Group
6-61
1997-10-01
On-Chip Peripheral Components C540U / C541U
The device interrupt request register DIRR contains the interrupt request flags of the different types of device interrupts. All Interrupt request flags in DIRR are reset by hardware after DIRR has been read. USB Device Interrupt Request Register DIRR (Address C4H) Bit No. C4H MSB 7 SE0I r Bit SE0I 6 DAI r Function Single ended zero interrupt Bit SE0I is set each time a single ended zero is detected for equal or greater than 2.5s. EOP (2 bit times) is not detected. Device attached interrupt Bit DAI is automatically set after detection of the USB device being attached to the USB bus. Device detached interrupt Bit DDI is automatically set after detection of the device being detached from the USB bus. Suspend begin interrupt Bit SBI is automatically set when the suspend mode is entered. Suspend end interrupt Bit SBI is automatically set when the suspend mode is left. Status interrupt Bit STI is set if the host requests a status transfer and the device answers with NACK (if bit ESP is set, the device answers with ACK and STI is not set). Setup interrupt Bit SUI is automatically set after a successful reception of a setup packet which is not handled by the USB module and must be forwarded to the CPU. The setup packet itself is limited to 8 bytes and is stored at USB memory adresses 00H to 07H and can be accessed with EPSEL.7=1. If a setup interrupt occurs (STI is set), the control and status bits UBF0, CBF0, SOD0, and DIR0 in the endpoint 0 registers EPBS0 and EPIR0 are cleared. DIR0=0 predicts the direction of the next USB access (data phase) to be from host to CPU. Bit DIR0 is automatically set (CPU to host), if the host tries to perform a read access in the first data packet. Start of frame Bit SOF is automatically set after detection of a start of frame packet on the USB. 5 DDI r 4 SBI r 3 SEI r 2 STI r 1 SUI r Reset Value : 00H LSB 0 SOFI r DIRR
DAI
DDI
SBI SEI STI
SUI
SOFI
Semiconductor Group
6-62
1997-10-01
On-Chip Peripheral Components C540U / C541U
The frame number registers stores an 11-bit value which defines the number of an USB frame. The frame number rolls over upon reaching its maximum value of 7FFH. The FNRH/FNRL registers are read only registers which are reset to 00H by a hardware reset. Frame Number Register High Byte FNRH (Address C7H) Frame Number Register Low Byte FNRL (Address C6H) Bit No. C7H MSB 7 0 r C6H FNR7 r Bit FNR10-0 Reset Value : 00000XXXB Reset Value : XXH LSB 0 FNR8 r FNR0 r FNRL FNRH
6 0 r FNR6 r
5 0 r FNR5 r
4 0 r FNR4 r
3 0 r FNR3 r
2 FNR10 r FNR2 r
1 FNR9 r FNR1 r
Function Frame number value FNRH.2-.0 and FNRL.7-.0 hold the current 11-bit frame number of the latest SOF token. FNRL holds the lowest 8 bits while FNRH holds the upper 3 bits of the frame number.
Semiconductor Group
6-63
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.4.7.3
Endpoint Registers
Each of the five endpoints has its own endpoint register set which contains the following registers (n=0-4) : - - - - - - EPBCn EPBSn EPIERn EPIRRn EPBAn EPLENn Endpoint n Buffer Control Register Endpoint n Buffer Status Register Endpoint n Interrupt Enable Register Endpoint n Interrupt Request Register Endpoint n Base Address Register Endpoint n Buffer Length Register
The endpoint buffer control registers control the endpoint specific operations. Endpoint 1 Buffer Control RegisterEPBCn, n=0-4 (Address C1H) Bit No. C1H MSB 7 STALLn rw Bit STALLn 6 0 r 5 0 r 4 3 2 1 0 r Reset Value : 00H LSB 0 DBMn rw EPBCn
GEPIEn SOFDEn INCEn rw rw rw
Function Endpoint stall Bit STALL can be set to indicate that the endpoint is stalled. If STALL=0, the endpoint n is active. If STALL=1, the endpoint n is stalled. Note : If the stall bit for endpoint 0 (STALL0) is set, the next incoming setup token will automatically clear it. Global endpoint interrupt enable Bit GEPIEn enables or disables the generation of the global endpoint interrupt n based on the endpoint specific interrupt request bits in register EPIRn. If GEPIE=0, the USB endpoint n interrupt is disabled. If GEPIE=1, the USB endpoint n interrupt is enabled. Start of frame done enable If bit SOFDE is set, the current CPU buffer in USB memory is automatically tagged full (data flow from the CPU to the USB) or empty (data flow from the USB to the CPU) on each detection of a start of frame on the USB (auto-done). If SOFDE=0, no action on SOF. If SOFDE=1, the automatical generation of DONE on SOF is enabled.
GEPIEn
SOFDEn
Semiconductor Group
6-64
1997-10-01
On-Chip Peripheral Components C540U / C541U
Bit INCEn
Function Auto increment enable If bit INCE is set, the address offset register ADROFF for CPU access to USB memory is automatically incremented after each data write or data read action of the USBVAL register. This allows the user to handle the USB memory like a FIFO without modification of the address of the desired memory location by software. After each modification of ADROFF the data value pointed to is automatically read out of USB memory and transferred to the USBVAL register. If INCE=0, the auto-increment function is disabled. If INCE=1, the auto-increment function is enabled. Dual buffer mode Bit DBM allows the selection between single buffer mode and dual buffer mode. If DBM=0, single buffer mode is selected. If DBM=1, dual buffer mode is selected.
DBMn
Note: For accessing the EPBCn registers SFR EPSEL(D2H) must be set with the appropriate value.
Semiconductor Group
6-65
1997-10-01
On-Chip Peripheral Components C540U / C541U
The bits of the endpoint buffer status registers indicate the status of the endpoint specific USB memory buffers and allows setting of certain USB memory buffer conditions. Endpoint Buffer Status Register EPBSn, n=0-4 (Address C2H) Bit No. C2H MSB 7 UBFn r Bit UBFn Reset Value : 20H LSB 0 EPBSn
6 CBFn r
5 DIRn r
4
3
2
1
ESPn SETRDn SETWRn CLREPn DONEn w w w w w
Function USB buffer full Bit UBFn indicates the status of the USB memory buffer for endpoint n. USB read access: If UBFn=0, the USB buffer for endpoint n is empty. If UBFn=1, the USB buffer for endpoint n is not empty. USB write access : If UBFn=0, the USB buffer for endpoint n is not full. If UBFn=1, the USB buffer for endpoint n is full. CPU buffer full Bit CBFn indicates the status of the CPU memory buffer for endpoint n. CPU read access: If CBFn=0, the CPU buffer for endpoint n is empty. If CBFn=1, the CPU buffer for endpoint n is not empty. CPU write access: If CBFn=0, the CPU buffer for endpoint n is not full. If CBFn=1, the CPU buffer for endpoint n is full. Direction of USB memory access Bit DIRn indicates the direction of the last USB memory access for endpoint n. If DIRn=0, the last data flow for endpoint n was from host to CPU. If DIRn=1, the last data flow for endpoint n was from CPU to host. Enable status phase If bit ESPn is set, the next status phase of endpoint n will automatically be acknowledged by an ACK except the endpoint n is stalled. If the status phase was successfully completed, bit ESPn is automatically reset by hardware and no status interrupt request (STI) is generated. If the CPU detects a corrupted control transfer (endpoint 0), bit STALL0 should be set by software instead of bit ESP0 in order to indicate an error condition which cannot be recovered by the USB device itself. Note : bit EPSn can only be set by software. Any read operation of register EPBSn returns ESPn=0. Set direction of USB memory buffer to read Bit SETRDn is used to predict the direction of the next USB access for endpoint n as an USB read access. A faulty prediction causes no errors since the USB module determines the real direction. A change in the data direction is only executed, if both USB memory buffers are empty. SETRD cannot be set together with CLREPn because a change of bit DIRn during a transfer is not allowed. Note : bits SETRDn and SETWRn must not be set at a time.
CBFn
DIRn
ESPn
SETRDn
Semiconductor Group
6-66
1997-10-01
On-Chip Peripheral Components C540U / C541U
Bit SETWRn
Function Set direction of USB memory buffer to write Bit SETWRn is used to predict the direction of the next USB access for endpoint n as an USB write access. A faulty prediction causes no errors since the USB module determines the real direction. A change in the data direction is only executed, if both USB memory buffers are empty. SETWR cannot be set together with CLREPn because a change of bit DIRn during a transfer is not allowed. Note : bits SETWRn and SETRDn must not be set at a time. Clear endpoint Setting bit CLREPn will set the address offset register for a CPU access to USB memory to 0. The bits CBFn and UBFn will be reset when CLREPn is set. Bit CLREPn is reset by hardware. A read operation on this bit will always deliver 0. Setting of CLREPn does not change the direction of endpoint n. This means, bit DIRn is not changed. Note: When bits CLREPn and ESPn are set simultaneously with one instruction, bit ESPn remains set and the next status phase is enabled. If only CLREPn is set, bit ESPn is reset and the status phase is disabled. Setting bits CLREPn and SETRDn or SETWRn simultaneously with one instruction is not allowed. This means that the information of SETRDn or SETWRn is ignored in this case. Buffer done by CPU If bit DONE is set, the current USB memory buffer assigned to CPU is automatically tagged full (data flow from the CPU to the USB) or empty (data flow from the USB to the CPU). This bit is reset by hardware after it has been set. A read operation on this bit will deliver always 0. Note: If the direction of endpoint n is read (USB read access) and auto-increment is enabled (INCEn=1) and DONEn is set the content of register ADROFF is copied automatically to register EPLENn of the actual endpoint. Register EPLENn is not changed if the auto-increment capability is disabled (INCEn=0).
CLREPn
DONEn
Semiconductor Group
6-67
1997-10-01
On-Chip Peripheral Components C540U / C541U
The endpoint interrupt enable registers contain the endpoint specific interrupt enable bits. With these bits, the endpoint specific interrupts can be individually enabled or disabled. Additionally to a bit in an EPIEn register, the global interrupt bit EPIn in GEPIR for endpoint n and the general endpoint interrupt bit EUEI in IEN1 and the general interrupt enable bit EA in IEN0 must be set for the interrupt becoming active. Endpoint Interrupt Enable Register EPIEn, n=0-4 (Address C3H) Bit No. C3H MSB 7 AIEn rw Reset Value : 00H LSB 6 5 4 - rw 3 2 1 0 EPIEn
NAIEn RLEIEn rw rw
DNRIEn NODIEn EODIEn SODIEn rw rw rw rw
For accessing EPIEn, SFR EPSEL must be 0nH. Bit AIEn Function USB acknowledge interrupt enable Bit AIEn enables the generation of an endpoint specific acknowledge interrupt when bit ACKn in register EPIRn is set. If AIEn=0, the USB acknowledge interrupt is disabled. If AIEn=1, the USB acknowledge interrupt is enabled. USB not acknowledged interrupt enable Bit NAIEn enables the generation of an endpoint specific not acknowledged interrupt when bit NACKn in register EPIRn is set. If NAIEn=0, the USB not acknowledged interrupt is disabled. If NAIEn=1, the USB not acknowledged interrupt is enabled. Read length error interrupt enable Bit RLEIEn enables the generation of an endpoint specific read length error interrupt when bit RLEn in register EPIRn is set. If RLEIEn=0, the read length error interrupt is disabled. If RLEIEn=1, the read length error interrupt is enabled. Reserved bit for future use. Data not ready interrupt enable Bit DNRIEn enables the generation of an endpoint specific data not ready interrupt when bit DNRn in register EPIRn is set. If DNRIEn=0, the data not ready interrupt is disabled. If DNRIEn=1, the data not ready interrupt is enabled. No data interrupt enable Bit NODIEn enables the generation of an endpoint specific no data interrupt when bit NODn in register EPIRn is set. If NODIEn=0, the no data interrupt is disabled. If NODIEn=1, the no data interrupt is enabled.
NAIEn
RLEIEn
- DNRIEn
NODIEn
Semiconductor Group
6-68
1997-10-01
On-Chip Peripheral Components C540U / C541U
Bit EODIEn
Function End of data interrupt enable Bit EODIEn enables the generation of an endpoint specific end of data interrupt when bit EODn in register EPIRn is set. If EODIEn=0, the end of data interrupt is disabled. If EODIEn=1, the end of data interrupt is enabled. Start of data interrupt enable Bit SODIEn enables the generation of an endpoint specific start of data interrupt when bit SODn in register EPIRn is set. If SODIEn=0, the start of data interrupt is disabled. If SODIEn=1, the start of data interrupt is enabled.
SODIEn
Semiconductor Group
6-69
1997-10-01
On-Chip Peripheral Components C540U / C541U
The endpoint interrupt request register EPIRn contains the interrupt request flags of the different endpoint specific interrupts. In general, the bits in EPIRn are reset by hardware after a EPIRn read operation. Endpoint Interrupt Request Register EPIRn, n=0-4 (Address C4H) Reset Value EPIR0 : 11H Reset Value EPIR1 to EPIR4 : 10H Bit No. C4H MSB 7 ACKn r LSB 0 SODn r EPIRn
6 NACKn r
5 RLEn r
4 - r
3 DNRn r
2 NODn r
1 EODn r
For accessing EPIRn, SFR EPSEL must be 0nH. Bit ACKn NACKn RLEn Function USB acknowledge Bit ACKn=1 indicates a succesful action on the USB. USB not acknowledged Bit NACKn is set for all unsuccessful actions on the USB. Read length error Bit RLEn is automatically set if the number of bytes read by the USB does not correspond to the packet length programmed by the CPU. Reserved bit for future use. Data not ready This bit is set by hardware if the UDC requires an access to USB memory, but no buffer is available. USB Read action : DNRn is set if UBF is not set. USB Write action : DNRn is set if UBF is set. No data This bit indicates an incorrect CPU read or write access to USB memory. It is set if the CPU processes a read access to an empty USB buffer or a write access to a full buffer. NODn is also set if the direction is write (DIRn=0 for USB write access) and the CPU tries to write to the USB memory buffer. End of data USB Read action : EODn is set if the CPU has written a programmable number (MaxLen) of bytes in the transmit buffer. As a result, the buffer is full and no more write actions from the CPU are allowed. USB Write action: EODn is set if the CPU has read a programmable number (USBLen) of bytes out of the receive buffer. As a result, the buffer is empty now and no more read actions from the CPU are allowed.
- DNRn
NODn
EODn
Semiconductor Group
6-70
1997-10-01
On-Chip Peripheral Components C540U / C541U
Bit SODn
Function Start of data USB Read action: SODn is set if the USB has read a fixed number (USBLen) of bytes from the transmit buffer. As a result, the buffer is empty now and the CPU can process write actions again. USB Write action: SODn is set if the USB has written a fixed number (USBLen) of bytes to the receive buffer. As a result, the buffer is full and the CPU can start read actions..
In dual buffer mode bits SODn and EODn can be set simultaneously if the corresponding buffer page is swapped.
Semiconductor Group
6-71
1997-10-01
On-Chip Peripheral Components C540U / C541U
The endpoint base address register defines the location and size (start address and length) of the endpoint specific buffers in the USB memory. See also figure 6-38 for an example of EPBAn and EPLENn register setup. Endpoint n Base Address Register EPBAn, n=0-4 (Address C5H) Reset Value : 00H Endpoint n Buffer Length Register EPLENn, n=0-4 (Address C6H) Reset Val.: 0XXXXXXXB Bit No. C5H MSB 7 PAGEn r C6H 0 r LSB 0 An3 rw Ln0 rw EPLENn EPBAn
6 0 r Ln6 rw
5 0 r Ln5 rw
4 0 r Ln4 rw
3 An6 rw Ln3 rw
2 An5 rw Ln2 rw
1 An4 rw Ln1 rw
Bit PAGEn
Function Buffer page for endpoint n (single buffer mode only) In single buffer mode, the endpoint n can be either located on USB memory buffer page 0 (PAGEn=0) or on USB memory buffer page 1 (PAGEn=1) by clearing or setting this bit. In dual buffer mode this bit has no effect. Note: The SETUP token is always stored on USB memory buffer page 0 at address 00H to 07H. Endpoint n buffer start address The bits 0 to 3 of EPBAn are the address bits A6 to A3 of the USB memory buffer start address for endpoint n. A7 and A2-A0 of the resulting USB memory buffer start address are set to 0. Endpoint n buffer length The bits 0 to 6 if EPLENn define the length of the USB memory buffer for endpoint n and cannot be written if DINIT=1.
An6-An3
Ln6-Ln0
The USB buffer allocation and organization is described in detail in section 6.4.3.
Semiconductor Group
6-72
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.4.8 On-Chip USB Transceiver The C540U/C541U provides on-chip receiver and transmitter circuitries which allows to connect the C540U/C541U directly to the USB bus. The USB driver circuitry is shown in figure 6-42. The USB transceiver is capable of transmitting and receiving serial date at full speed (12 MBits/s) and low speed (1.5 Mbit/s) data rates. Transceiver and receiver can be separately disabled for power down mode operation. A single ended zero error condition (D+ and D- both at low level) can be detected.
1 0 TPWD DPWDR.1 Transmit Data
30 D+ Pin 30 DPin
Receive Data 1 0 RPWD DPWDR.0
+
MCS03413
Figure 6-42 USB On-chip Driver Circuitry The USB driver circuitry is a differential output driver which drives the USB data signal onto the cable of the USB bus. The static output swing of the transmitter is in low state below 0.3 V with a 1.5 k load to 3.6 V and in high state above 2.8 V with a 15 k load to VSS. The driver outputs support tri-state operation to achieve bi-directional half duplex operation (control bits RPWD and TPWD). High impedance is also required to isolate the port from devices that are connected but powered down. The driver tolerates a voltage on the signal pins of -0.5 V to 3.8 V with respect to local ground reference without damage. This voltage is tolerated for 10.0 s while the driver is active and driving, When the driver is in its high impedance state it tolerates this condition an indefinitely long time. For a full speed USB connection the impedance of the USB driver must be between 29 and 44 . The data line rise and fall times are between 4 ns and 20 ns, smoothly rising or falling (monotonic), and are well matched to minimize RFI emissions and signal skew. Figure 6-42 shows how the full speed driver is realized using two identical CMOS buffers. Figure 6-43 shows the full speed driver signal waveforms. Semiconductor Group 6-73 1997-10-01
On-Chip Peripheral Components C540U / C541U
One Bit Time (12 MB/s)
Driver Signal Pins
V SS
One-Way Trip Cable Delay
Receiver Signal Pins
V SE max V SE min V SS
Signal Pins Pass Input Spec Levels after one Cable Delay
MCT03414
Figure 6-43 Full Speed USB Driver Signal Waveforms For a low speed USB connection the rise and fall time of the signals are greater than 75 ns to keep RFI emissions under FCC class B limits, and less than 300 ns to limit timing delays and signaling skews and distortions. The driver reaches the specified static signal levels with smooth rise and fall times, and minimal reflections and ringing when driving the USB cable (see figure 6-44). This cable and driver are used only on network segments between low speed devices and the ports to which they are connected.
One Bit Time (1.5 MB/s)
Driver Signal Pins
V SE max V SE min V SS
Signal Pins Pass Output Spec Levels with minimal Reflections and ringing
MCT03415
Figure 6-44 Low Speed USB Driver Signal Waveforms
Semiconductor Group
6-74
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.4.9
Detection of Connected Devices
Full speed and low speed USB devices are differentiated by the position of the pullup resistor on the downstream end of the cable. Full speed devices are terminated with the pull-up on the D+ line and low speed devices are terminated with the pull-up in the D- line (see figure 6-). The pull-up terminator is a 1.5 k resistor tied to a voltage source between 3.0 and 3.6 V referenced to the local ground. When a device is attached to the host or hub, the data line with the pull-up is above 2.8 V and the other data line is near ground (idle state). A connect condition will be detected when one of the data lines is pulled above the single-ended high threshold level for more than 2.5 s (30 full speed data bit times). When a device is detached from the USB, the pull-down resistors will cause both D+ and D- lines to be pulled below the single-ended low threshold of the host or hub port. This creates a state called a single-ended zero (SE0) on the downstream port. A disconnect condition is indicated if an SE0 persists on a downstream port for more than 2.5 s (30 full speed data bit times).
R2
D+ FS / LS USB Transceiver DHost or Hub Port D+ Twisted Pair Shielded 5 meters max. FS / LS USB D- Transceiver Full Speed Device
R1
R1
R2
D+ FS / LS USB Transceiver DHost or Hub Port D+ Unwisted, Unshielded 3 meters max. FS / LS USB D- Transceiver Low Speed Device
MCS03416
R1
R1
Figure 6-45 Low Speed / High Speed Device Cable and Resisitor Connection Resistor R2 has to be external. In some cases it might be necessary to hide the USB device from the host even when it is plugged in. To accomplish this, the pull-up resistor R2 can be made switchable with a port a transistor.
Semiconductor Group
6-75
1997-10-01
On-Chip Peripheral Components C540U / C541U
6.4.10 Detach / Attach Detection The USB device can be used in two different modes concerning its power supply, the bus-powered mode and the self-powered mode. 6.4.10.1 Self-Powered Mode In self-powered mode, the USB device has its own power supply. The USB device has to detect whether it is connected to USB bus or not. This detection is done by hardware by using the DeviceAttached Device-Detached pin DADD as shown in figure 6-46. When the device-attached condition is detected, bit DA in the device control register DCR is set and a device interrupt can be generated if required (bit DAI in SFR DIRR is set). The interrupt service routine of this device interrupt must completely initialize the USB device/module. The device-detached detection resets bit DA (and sets bit DDI in SFR DIRR) and can generate a device interrupt, too.
V CC
P3.1 / DADD 5 k 47 nF 100 k N-Channel FET C540U C541U
V SS
MCS03417
Figure 6-46 Device Attached - Device Detached detection in self-powered mode 6.4.10.2 Bus-Powered Mode In bus-powered mode, the USB device is driven by the power supply from the USB bus. The maximum power consumption is given by the USB specification. In order to respect this specification, the power consumption in suspend mode should not exceed 500 A. An explicit device-attached detection in this mode is not necessary. If the CPU is running, the device is attached, so the USB device/module has to be configured only after power-on. The device-detach action has no significance concerning software, because the device is no longer powered and the CPU stops. As a result, no attach-detach detection is needed. In this mode, pin DADD can be used as standard IO pin with bit DA monitoring its status and the interrupt generation on DA should not be used. If the interrupt generation on bit DA remains activated, a request must not be interpreted as attached-detached action, but as an external interrupt request on pin DADD, which is generating a device interrupt.
Semiconductor Group
6-76
1997-10-01
Interrupt System C540U / C541U
7
Interrupt System
The C541U provides seven (C540U : six) interrupt sources with two priority levels. Five interrupts can be generated by the on-chip peripherals (timer 0, timer 1, SSC interface, and USB module), and two interrupts may be triggered externally (P3.2/INT0 and P3.3/INT1). Figure 7-47 and 7-48 give a general overview of the interrupt sources and illustrate the request and control flags which are described in the next sections.
Low Priority Timer 0 Overflow TF0 TCON.5 ET0 IEN0.1 Timer 1 Overflow TF1 TCON.7 ET1 IEN0.3 P3.2 / INT0 IT0 TCON.0 ITCON.1 ITCON.0 1 IE0 TCON.1 EX0 IEN0.0 0003H PX0 IP0.0 001BH PT1 IP0.3 000BH PT0 IP0.1 High Priority
P3.3 / INT1 IT1 TCON.2 ITCON.3 Bit addressable ITCON.2
1 IE0 TCON.3 EX1 IEN0.2 EA IEN0.7 0013H PX1 IP0.2
Request Flag is cleared by hardware
Figure 7-47 Interrupt Request Sources (Part 1)
Semiconductor Group
7-1
1997-10-01
Interrupt System C540U / C541U
Endpoint Interrupts
Endpoint 4 Interrupts Endpoint 3 Interrupts Endpoint 2 Interrupts Endpoint 1 Interrupts Endpoint 0 Interrupts ACK0 EPIR0.7
NACK0
AIE0 EPIE0.7 NAIE0 EPIE0.6 RLEIE0 EPIE0.5 DNRIE0 EPIE0.3 NODIE0 EPIE0.2 EODIE0 EPIE0.1 SODIE0 EPIE0.0 GEPIE0
EPIR0.6 RLE0 EPIR0.5 DNR0 EPIR0.3 NOD0 EPIR0.2 EOD0 EPIR0.1 SOD0 EPIR0.0
>1 EPI0 GEPIR.0 >1 Low Priority High Priority EUEI IEN1.1 EPBC0.4 004B H PUEI IP1.1
WCOL SSC Interrupts (C541U only) SCF.1 WCEN SCIEN.1 ESSC TC SCF.0 Bit addressable Request flag is cleared by hardware after the corresponding register has been read.
MCB03382
>1
0043 H PSSC EA IEN0.7 IP1.0
IEN1.0 TCEN SCIEN.0
Figure 7-48 Interrupt Request Sources (Part 2)
Semiconductor Group
7-2
1997-10-01
Interrupt System C540U / C541U
Device Interrupts
SE0I DIRR.7 DAI DIRR.6 DDI DIRR.5 SBI DIRR.4 SEI DIRR.3 STI DIRR.2 SUI DIRR.1 SOFI DIRR.0
SE0IE DIER.7 DAIE DIER.6 DDIE DIER.5 SBIE DIER.4 SEIE DIER.3 STIE DIER.2 SUIE DIER.1 SOFIE DIER.0
>1 Low Priority High Priority EUDI IE1.2 0053 H PUDI IP1.2
EA IE0.7
Bit addressable Request flag is cleared by hardware after the corresponding register has been read.
MCB03383
Figure 7-49 Interrupt Request Sources (Part 3)
Semiconductor Group
7-3
1997-10-01
Interrupt System C540U / C541U
7.1
Interrupt Registers
7.1.1 Interrupt Enable Registers Each interrupt vector can be individually enabled or disabled by setting or clearing the corresponding bit in the interrupt enable registers IEN0 or IEN1. Register IEN0 also contains the global disable bit (EA), which can be cleared to disable all interrupts at once. The SSC and USB interrupts sources have further enable bits for individual interrupt control. Such interrupt enable bits are controlled by specific bits in the SFRs of the corresponding peripheral units. The IEN0 register contains the general enable/disable flags of the external interrupts 0 and 1 as well as the timer interrupts. The SSC interrupt (C540U only) and the two USB interrupts are enabled/ disabled by bits in the IEN1 register. After reset the enable bits of IEN0 and IEN1 are set to 0. That means that the corresponding interrupts are disabled.
Special Function Registers IEN0 (Address A8H) Bit No. MSB AFH A8H EA AEH - ADH - ACH - ABH ET1 AAH EX1
Reset Value : 0XXX0000B LSB A9H ET0 A8H EX0 IEN0
Bit EA
Function Enable/disable all Interrupts If EA=0, no interrupt will be acknowledged. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. Not implemented. Reserved for future use. Timer 1 overflow interrupt enable If ET1 = 0, the timer 1 interrupt is disabled If ET1 = 1, the timer 1 interrupt is enabled. External interrupt 1 enable If EX1 = 0, the external interrupt 1 is disabled. If EX1 = 1, the external interrupt 1 is enabled. Timer 0 overflow interrupt enable If ET0 = 0, the timer 0 interrupt is disabled If ET0 = 1, the timer 0 interrupt is enabled. External interrupt 0 enable If EX0 = 0, the external interrupt 0 is disabled. If EX0 = 1, the external interrupt 0 is enabled.
- ET1
EX1
ET0
EX0
Semiconductor Group
7-4
1997-10-01
Interrupt System C540U / C541U
Special Function Registers IEN1 (Address A9H) Special Function Registers SCIEN (C541U only, Address ACH) Bit No. A9H MSB 7 -
Reset Value : XXXXX000B Reset Value : XXXXXX00B LSB
6 -
5 -
4 -
3 -
2 EUDI
1 EUEI
0 ESSC IEN1
ACH
-
-
-
-
-
-
WCEN
TCEN
SCIEN
Bit - EUDI
Function Not implemented. Reserved for future use. Enable USB device interrupt enable If EUDI = 0, the general USB device interrupt is disabled. If EUDI = 1, the general USB device interrupt is enabled. Enablel USB endpoint interrupt If EUEI = 0, the general USB endpoint interrupt is disabled. If EUEI = 1, the general USB endpoint interrupt is enabled. SSC general interrupt enable (C541U only) If ESSC = 0, the SSC general interrupt is disabled. If ESSC = 1, the SSC general interrupt is enabled. SSC write collision interrupt enable (C541U only) If WCEN = 0, the SSC write collision interrupt is disabled. If WCEN = 1, the SSC write collison interrupt is enabled. Additionally, bit ESSC must be set if the SSC write collision interrupt should be generated. SSC transfer completed interrupt enable (C541U only) If TCEN = 0, the SSC transfer completed interrupt is disabled. If TCEN = 1, the SSC transfer completed interrupt is enabled. Additionally, bit ESSC must be set if the SSC transfer completed interrupt should be generated.
EUEI
ESSC
WCEN
TCEN
Semiconductor Group
7-5
1997-10-01
Interrupt System C540U / C541U
Special Function Registers DIER (Address C3H) Bit No. C3H MSB 7 SE0IE
Reset Value : 00H LSB
6 DAIE
5 DDIE
4 SBIE
3 SEIE
2 STIE
1 SUIE
0 SOFIE DIER
For accessing DIER, SFR EPSEL must be 80H. Bit SE0IE Function USB single ended zero interrupt enable If SE0IE=0, the single ended zero interrupt is disabled. If SE0IE=1, the single ended zero interrupt is enabled USB device attached interrupt enable If DAIE=0, the USB device attached interrupt is disabled. If DAIE=1, the USB device attached interrupt is enabled. USB device detached interrupt enable If DDIE=0, the USB device detached interrupt is disabled. If DDIE=1, the USB device detached interrupt is enabled. USB suspend begin interrupt enable If SBIE=0, the USB suspend begin interrupt is disabled. If SBIE=1, the USB suspend begin interrupt is enabled. USB suspend change interrupt enable If SEIE=0, the USB suspend change interrupt is disabled. If SEIE=1, the USB suspend change interrupt is enabled. USB status interrupt enable If STIE=0, the USB status interrupt is disabled. If STIE=1, the USB status interrupt is enabled. USB setup interrupt enable If SUIE=0, the USB setup interrupt is disabled. If SUIE=1, the USB setup interrupt is enabled. USB start of frame interrupt enable If SOFIE=0, the USB start of frame interrupt is disabled. If SOFIE=1, the USB start of frame interrupt is enabled.
DAIE
DDIE
SBIE
SEIE
STIE
SUIE
SOFIE
Semiconductor Group
7-6
1997-10-01
Interrupt System C540U / C541U
Special Function Registers EPIEn, n=0-4 (Address C3H) Bit No. MSB 7 AIEn
Reset Value : 00H LSB
6
5
4 -
3
2
1
0 EPIEn
C3H
NAIEn RLEIEn
DNRIEn NODIEn EODIEn SODIEn
For accessing EPIEn, SFR EPSEL must be 0nH. Bit AIEn Function USB acknowledge interrupt enable If AIEn=0, the USB acknowledge interrupt is disabled. If AIEn=1, the USB acknowledge interrupt is enabled. USB not acknowledged interrupt enable If NAIEn=0, the USB not acknowledged interrupt is disabled. If NAIEn=1, the USB not acknowledged interrupt is enabled. USB read length error interrupt enable If RLEIEn=0, the USB read length error interrupt is disabled. If RLEIEn=1, the USB read length error interrupt is enabled. Reserved bit for future use. USB data not ready interrupt enable If DNRIEn=0, the USB data not ready interrupt is disabled. If DNRIEn=1, the USB data not ready interrupt is enabled. USB nodata interrupt enable If NODIEn=0, the USB no data interrupt is disabled. If NODIEn=1, the USB no data interrupt is enabled. USB end of data interrupt enable If EODIEn=0, the USB end of data interrupt is disabled. If EODIEn=1, the USB end of data interrupt is enabled. USB start of data interrupt enable If SODIEn=0, the USB start of data interrupt is disabled. If SODIEn=1, the USB start of data interrupt is enabled.
NAIEn
RLEIEn
- DNRIEn
NODIEn
EODIEn
SODIEn
Semiconductor Group
7-7
1997-10-01
Interrupt System C540U / C541U
Endpoint n Buffer Control RegisterEPBCn, n=0-4 (Address C1H) Bit No. C1H MSB 7 STALLn rw 6 0 r 5 0 r 4 3 2 1 0 r
Reset Value : 00H LSB 0 DBMn rw EPBCn
GEPIEn SOFDEn INCEn rw rw rw
The shaded bits are not used for interrupt control.
Bit GEPIEn
Function Global endpoint interrupt enable Bit GEPIEn enables or disables the generation of the global endpoint interrupt forr endpoint n based on the endpoint specific interrupt request bits in register EPIRn. If GEPIEn=0, the USB endpoint n interrupt is disabled. If GEPIEn=1, the USB endpoint n interrupt is enabled.
Note: For accessing the EPBCn registers SFR EPSEL(D2H) must be set with the appropriate value.
Semiconductor Group
7-8
1997-10-01
Interrupt System C540U / C541U
7.1.2 Interrupt Request / Control Flags The external interrupts 0 and 1 (INT0 and INT1) can each be either level-activated or negative transition-activated, depending on bits IT0 and IT1 in register TCON. The flags that actually generate these interrupts are bits IE0 and lE1 in TCON. When an external interrupt is generated, the flag that generated this interrupt is cleared by the hardware when the service routine is vectored too, but only if the interrupt was transition-activated. lf the interrupt was level-activated, then the requesting external source directly controls the request flag, rather than the on-chip hardware. The timer 0 and timer 1 interrupts are generated by TF0 and TF1 in register TCON, which are set by a rollover in their respective timer/counter registers. When a timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored too. Special Function Register TCON (Address 88H) Bit No. 88H MSB 8FH TF1 8EH TR1 8DH TF0 8CH TR0 8BH IE1 8AH IT1 89H IE0 Reset Value : 00H LSB 88H IT0 TCON
The shaded bits are not used for interrupt control.
Bit TF1
Function Timer 1 overflow flag Set by hardware on timer/counter 1 overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 0 overflow flag Set by hardware on timer/counter 0 overflow. Cleared by hardware when processor vectors to interrupt routine. External interrupt 1 request flag Set by hardware when external interrupt 1 edge is detected. Cleared by hardware when processor vectors to interrupt routine. External interrupt 1 level/edge trigger control flag If IT1 = 0, low level triggered external interrupt 1 is selected. If IT1 = 1, edge triggered mode for external interrupt 1 is selected. The bits IE1TR and IE1TF in SFR ITCON (see section 7.4) further define which signal transition at pin INT1 (rising and/or falling edge) generates an interrupt. External interrupt 0 request flag Set by hardware when external interrupt 0 edge is detected. Cleared by hardware when processor vectors to interrupt routine. External interrupt 0 level/edge trigger control flag If IT0 = 0, low level triggered external interrupt 0 is selected. If IT0 = 1, edge triggered mode for external interrupt 0 is selected. The bits IE0TR and IE0TF in SFR ITCON (see section 7.4) further define which signal transition at pin INT0 (rising and/or falling edge) generates an interrupt.
TF0
IE1
IT1
IE0
IT0
Semiconductor Group
7-9
1997-10-01
Interrupt System C540U / C541U
Special Function Register SCF (C541U only, Address ABH) MSB 7 -
Reset Value : XXXXXX00B LSB 0 TC SCF
Bit No. ABH
6 -
5 -
4 -
3 -
2 -
1 WCOL
Bit - WCOL
Function Reserved bits for future use. SSC write collision interrupt flag WCOL set indicates that an attempt was made to write to the shift register STB while a data transfer was in progress and not fully completed. Bit WCEN in the SCIEN register must be set, if an interrupt request will be generated when WCOL is set. SSC transfer complete interrupt flag If TC is set it indicates that the last transfer has been completed. Bit TCEN in the SCIEN register must be set, if an interrupt request will be generated when TC is set.
TC
The SSC interrupt is generated by a logical OR of flag WCOL and TC in SFR SCF. Both bits can be cleared by software when a "0" is written to the bit location. WCOL is reset by hardware when after a preceeding read operation of the SCF register the SSC transmit data register STB is written with data. TC is reset by hardware when after a preceeding read operation of the SCF register the receive data register SRB is read the next time. The interrupt service routine will normally have to determine whether it was the WCOL or the TC flag that generated the interrupt, and the bit will have to be cleared by software.
Semiconductor Group
7-10
1997-10-01
Interrupt System C540U / C541U
The USB device interrupt request register contains the device specific interrupt flags of the USB module. These flags describe special events of the USB module. If a request flag is set, it is automatically cleared after a read operation of the DIRR register. Special Function Registers DIRR (Address C4H) Bit No. C4H MSB 7 SE0I Reset Value : 00H LSB 6 DAI 5 DDI 4 SBI 3 SEI 2 STI 1 SUI 0 SOFI DIRR
For accessing DIRR, SFR EPSEL must be 80H. Bit SE0I Function Single ended zero interrupt Bit SE0I is set each time a single ended zero is detected for equal or greater than 2.5s. EOP (2 bit times) is not detected. Device attached interrupt Bit DAI is automatically set after detection of the USB device being attached to the USB bus. Device detached interrupt Bit DDI is automatically set after detection of the device being detached from the USB bus. Suspend begin interrupt Bit SBI is automatically set when the suspend mode is entered. Suspend end interrupt Bit SBI is automatically set when the suspend mode is left. Status interrupt Bit STI is set if the host requests a status transfer and the device answers with NACK. Setup interrupt Bit SUI is automatically set after a successful reception of a setup packet. Start of frame Bit SOF is automatically set after detection of a start of frame packet on the USB.
DAI
DDI
SBI SEI STI
SUI SOFI
Semiconductor Group
7-11
1997-10-01
Interrupt System C540U / C541U
The register EPIRn (n=0-4) contains USB endpoint specific interrupt request flags. This SFR is availble for each endpoint. If a request flag in EPIRn is set, it is automatically cleared after a read operation of the EPIRn register. Endpoint Interrupt Request Register EPIRn, n=0-4 (Address C4H) Reset Value EPIR0 : 11H Reset Value EPIR1 to EPIR4 : 10H Bit No. C4H MSB 7 ACKn r LSB 0 SODn r EPIRn
6 NACKn r
5 RLEn r
4 - r
3 DNRn r
2 NODn r
1 EODn r
For accessing EPIRn, SFR EPSEL must be 0nH. Bit ACKn NACKn RLEn Function USB acknowledge Bit ACKn=1 indicates a succesful action on the USB. USB not acknowledge Bit NACK is set for all unsuccessful actions on the USB. Read length error Bit RLEn is automatically set if the number of bytes read by the USB does not correspond to the packet length programmed by the CPU. Reserved bit for future use; Data not ready This bit is set by hardware if the USB module requires an access to USB memory, but no buffer is available. No data This bit indicates an incorrect CPU read or write access to USB memory. End of data During an USB read access EOD is set if the CPU has written a programmable number of bytes in the transmit buffer. During an USB write access EOD is set if the CPU has read a programmable number of bytes out of the receive buffer. Start of data During an USB read access SOD is set if the USB has read a fixed number of bytes from the transmit buffer. During an USB write access SOD is set if the USB has written a fixed number of bytes to the receive buffer.
- DNRn
NODn EODn
SODn
Semiconductor Group
7-12
1997-10-01
Interrupt System C540U / C541U
The global endpoint interrupt request register GEPIRn (n=0-4) contains one flag for each endpoint which indicates whether one or more of the seven endpoint specific interrupt requests has become active. If a request flag in GEPIR is set, it is automatically cleared after a read operation of the GEPIR register. USB Global Endpoint Interrupt Request Register GEPIR (Address D6H) Bit No. D6H MSB 7 0 r Bit EPI4 EPI3 EPI2 EPI1 EPI0 6 0 r Function Endpoint 4 interrupt request flag If EPI4 is set, an endpoint 4 interrupt request is pending. Endpoint 3 interrupt request flag If EPI3 is set, an endpoint 3 interrupt request is pending. Endpoint 2 interrupt request flag If EPI2 is set, an endpoint 2 interrupt request is pending. Endpoint 1 interrupt request flag If EPI1 is set, an endpoint 1 interrupt request is pending. Endpoint 0 interrupt request flag If EPI0 is set, an endpoint 0 interrupt request is pending. 5 0 r 4 EPI4 r 3 EPI3 r 2 EPI2 r 1 EPI1 r Reset Value : 00H LSB 0 EPI0 r GEPIR
Semiconductor Group
7-13
1997-10-01
Interrupt System C540U / C541U
7.1.3 Interrupt Prioritiy Registers Each interrupt source can also be individually programmed to one of two priority levels by setting or clearing a bit in the SFRs IP0 or IP1 (interrupt priority: 0 = low priority, 1 = high priority).
Special Function Registers IP0 (Address B8H) Special Function Registers IP1 (Address B9H) Bit No. B8H MSB 7 -
Reset Value : XXXX0000B Reset Value : XXXXX000B LSB 0 PX0 IP0
6 -
5 -
4 -
3 PT1
2 PX1
1 PT0
B9H
-
-
-
-
-
PUDI
PUEI
PSSC
IP1
Bit - PT1
Function Reserved for future use. Timer 1 overflow interrupt priority level If PT1 = 0, the timer 1 interrupt has a low priority. If PT1 = 1, the timer 1 interrupt has a high priority External interrupt 1 priority level If PX1 = 0, the external interrupt 1 has a low priority. If PX1 = 1, the external interrupt 1 has a high priority. Timer 0 overflow interrupt priority level If PT0 = 0, the timer 0 interrupt has a low priority. If PT0 = 1, the timer 0 interrupt has a high priority. External interrupt 0 priority level If PX0 = 0, the external interrupt 0 has a low priority. If PX0 = 1, the external interrupt 0 has a high priority. USB device interrupt priority level If PUDI = 0, the USB device interrupt has a low priority. If PUDI = 1, the USB device interrupt has a high priority. USB endpoint interrupt priority level If PUEI = 0, the USB endpoint interrupt has a low priority. If PUEI = 1, the USB endpoint interrupt has a high priority. SSC interrupt priority level (C541U only) If PSSC = 0, the SSC interrupt has a low priority. If PSSC = 1, the SSC interrupt has a high priority.
PX1
PT0
PX0
PUDI
PUEI
PSSC
Semiconductor Group
7-14
1997-10-01
Interrupt System C540U / C541U
7.2
Interrupt Priority Level Structure
A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another lowpriority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. If two requests of different priority level are received simultaneously, the request of higher priority is serviced. If requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus, within each priority level there is a second priority structure determined by the polling sequence (vertical and horizontal) as shown in table 7-12 below. If e.g. the external interrupt 0 and the SSC interrupt have the same priority and if they are active simultaneously, the external interrupt 0 will be serviced first. Table 7-12 Interrupt Source Structure Interrupt Source High Priority External Interrupt 0 Timer 0 Interrupt External Interrupt 1 Timer 1 Interrupt Priority Low Priority SSC Interrupt (C541U only) USB Endpoint Interrupt USB Device Interrupt - High
Low
Semiconductor Group
7-15
1997-10-01
Interrupt System C540U / C541U
7.3
How Interrupts are Handled
The interrupt flags are sampled at S5P2 in each machine cycle. The sampled flags are polled during the following machine cycle. If one of the flags was in a set condition at S5P2 of the preceeding cycle, the polling cycle will find it and the interrupt system will generate a LCALL to the appropriate service routine, provided this hardware-generated LCALL is not blocked by any of the following conditions: 1) An interrupt of equal or higher priority is already in progress. 2) The current (polling) cycle is not in the final cycle of the instruction in progress. 3) The instruction in progress is RETI or any write access to registers IE0/IE1 or IP0/IP1. Any of these three conditions will block the generation of the LCALL to the interrupt service routine. Condition 2 ensures that the instruction in progress is completed before vectoring to any service routine. Condition 3 ensures that if the instruction in progress is RETI or any write access to registers IEN0/IEN1 or IP0/IP1, then at least one more instruction will be executed before any interrupt is vectored too; this delay guarantees that changes of the interrupt status can be observed by the CPU. The polling cycle is repeated with each machine cycle, and the values polled are the values that were present at S5P2 of the previous machine cycle. Note that if any interrupt flag is active but not being responded to for one of the conditions already mentioned, or if the flag is no longer active when the blocking condition is removed, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag was once active but not serviced is not remembered. Every polling cycle interrogates only the pending interrupt requests. The polling cycle/LCALL sequence is illustrated in figure 7-50.
C1 S5P2
C2
C3
C4
C5
Interrupt is latched
Interrupts are polled
Long Call to Interrupt Vector Address
Interrupt Routine
MCT01859
Figure 7-50 Interrupt Response Timing Diagram
Semiconductor Group
7-16
1997-10-01
Interrupt System C540U / C541U
Note that if an interrupt of a higher priority level goes active prior to S5P2 in the machine cycle labeled C3 in figure 7-50 then, in accordance with the above rules, it will be vectored to during C5 and C6 without any instruction for the lower priority routine to be executed. Thus, the processor acknowledges an interrupt request by executing a hardware-generated LCALL to the appropriate servicing routine. In some cases it also clears the flag that generated the interrupt, while in other cases it does not; then this has to be done by the user's software. The hardware clears the external interrupt flags IE0 and IE1 only if they were transition-activated. The hardware-generated LCALL pushes the contents of the program counter onto the stack (but it does not save the PSW) and reloads the program counter with an address that depends on the source of the interrupt being vectored too, as shown in the following table 7-13. Table 7-13 Interrupt Source and Vectors Interrupt Source External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow SSC Interrupt (C541U only) USB Endpoint Interrupt USB Device Interrupt Wake-up from power down Interrupt Vector Address 0003H 000BH 0013H 001BH 0043H 004BH 0053H 007BH - Interrupt Request Flags IE0 TF0 IE1 TF1
Execution proceeds from that location until the RETI instruction is encountered. The RETI instruction informs the processor that the interrupt routine is no longer in progress, then pops the two top bytes from the stack and reloads the program counter. Execution of the interrupted program continues from the point where it was stopped. Note that the RETI instruction is very important because it informs the processor that the program left the current interrupt priority level. A simple RET instruction would also have returned execution to the interrupted program, but it would have left the interrupt control system thinking an interrupt was still in progress. In this case no interrupt of the same or lower priority level would be acknowledged. A special interrupt source is the power-down mode interrupt. This interrupt is automatically enabled when the C540U/C541U is in power-down mode and bit EWPD (enable wake-up from power-down mode) in SFR PCON1 is set. If these two conditions are met and when the oscillator watchdog unit start-up phase after a wake-up condition (INT0=0) is finished, the C540U/C541U starts with an interrupt at address 007BH. All other interrupts are now disabled until the RETI instruction of the power-down interrupt routine has been executed.
Semiconductor Group
7-17
1997-10-01
Interrupt System C540U / C541U
7.4
External Interrupts
The external interrupts 0 and 1 can be programmed to be level-activated or transition activated by setting or clearing bit IT0 or IT1 in register TCON. If ITx = 0 (x = 0 or 1), external interrupt x is triggered by a detected low level at the INTx pin. In edge-triggered mode (ITx = ) two bits of the ITCON register define the type of signal transition for which the external interrupt inputs are sensitive. Edge-triggered interrupt can be activated for an interrupt input signal at the rising edge, at the falling edge or at both signal transitions. In edge-triggered mode, if successive samples of the INTx pin show a different logic level in two consequent machine cycles, the corresponding interrupt request flag IEx in TCON is set. Flag bit IEx=1 then requests the interrupt. If the external interrupt 0 or 1 is level-activated, the external source has to hold the request active until the requested interrupt is actually generated. Then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. Since the external interrupt pins are sampled once in each machine cycle, an input high or low should be held for at least 6 oscillator periods to ensure sampling. lf the external interrupt is transition-activated, the external source has to hold the request pin high for at least one cycle, and then hold it low for at least one cycle to ensure that the transition is recognized so that the corresponding interrupt request flag will be set (see figure 7-51). The external interrupt request flags will automatically be cleared by the CPU when the service routine is called.
a) Level-Activated Interrupt
INTx > 1 Machine Cycle
Low-Level Threshold
b) Transition-Activated Interrupt High-Level Threshold INTx IxETF = 1 > 1 Machine Cycle Transition to be detected INTx IxETR = 1 Low-Level Threshold
MCT02577
> 1 Machine Cycle
Low-Level Threshold
High-Level Threshold
Figure 7-51 External Interrupt Detection Semiconductor Group 7-18 1997-10-01
Interrupt System C540U / C541U
The edge-triggered interrupt mode selection for the external interrupts is selected by bits in SFR ITCON (External Interrupt Trigger Condition Register). The edge-trigger mode selection is defined in a way (default value of ITCON after reset), that their function is upward compatible to the basic external interrupt functionality of the C501. Special Function Registers ITCON (Address 9AH) Bit No. MSB 7 9AH - 6 - 5 - 4 - 3 2 1 Reset Value : XXXX1010B LSB 0 ITCON I1ETF I1ETR I0ETF I0ETR INT1 Bit - IxETF IxETR Function Reserved bit for future use. External Interrupt Edge Trigger Mode Selection (x=0,1 refers to INT0, INT1) IxETF 0 0 1 1 IxETR Function 0 1 0 1 INTx inputs are not sensitive for either rising or falling edge INTx operates in rising edge-triggered mode INTx operates in falling edge-triggered mode (default after reset) INTx operates in falling and rising edge-triggered mode INT0
Semiconductor Group
7-19
1997-10-01
Interrupt System C540U / C541U
7.5
Interrupt Response Time
If an external interrupt is recognized, its corresponding request flag is set at S5P2 in every machine cycle. The value is not polled by the circuitry until the next machine cycle. If the request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be next instruction to be executed. The call itself takes two cycles. Thus a minimum of three complete machine cycles will elapse between activation and external interrupt request and the beginning of execution of the first instruction of the service routine. A longer response time would be obtained if the request was blocked by one of the three previously listed conditions. If an interrupt of equal or higer priority is already in progress, the additional wait time obviously depends on the nature of the other interrupt's service routine. If the instruction in progress is not in its final cycle, the additional wait time cannot be more than 3 cycles since the longest instructions (MUL and DIV) are only 4 cycles long; and, if the instruction in progress is RETI or a write access to registers IE or IP the additional wait time cannot be more than 5 cycles (a maximum of one more cycle to complete the instruction in progress, plus 4 cycles to complete the next instruction, if the instruction is MUL or DIV). Thus a single interrupt system, the response time is always more than 3 cycles and less than 9 cycles.
Semiconductor Group
7-20
1997-10-01
Fail Safe Mechanisms C540U / C541U
8
Fail Safe Mechanisms
The C540U/C541U offers enhanced fail safe mechanisms, which allow an automatic recovery from software upset or hardware failure : - a programmable watchdog timer (WDT), with variable time-out period from 256 s up to approx. 0.55 s at 12 MHz. The WDT is not available in the C540U. - an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for a fast internal reset after power-on. 8.1 Programmable Watchdog Timer (C541U only)
To protect the system against software upset, the user's program has to clear this watchdog within a previously programmed time period. lf the software fails to do this periodical refresh of the watchdog timer, an internal hardware reset will be initiated. The software can be designed so that the watchdog times out if the program does not work properly. lt also times out if a software error is based on hardware-related problems. The watchdog timer in the C541U is a 15-bit timer, which is incremented by a count rate of fOSC/12 or fOSC/192. The system clock of the C541U is divided by two prescalers, a divide-by-two and a divide-by-16 prescaler which are selected by bit WDTPSEL (WDTREL.7). For programming of the watchdog timer overflow rate, the upper 7 bit of the watchdog timer can be written. Figure 8-1 shows the block diagram of the watchdog timer unit.
0
7 WDTL 14 8 WDTH
f OSC / 6
2
16
WDT Reset-Request WDCON (CO H ) -
-
-
OWDS WDTS
WDT
SWDT
WDTPSEL
Control Logic 76 External HW Reset WDTREL
MCB03384
0
Figure 8-1 Block Diagram of the Programmable Watchdog Timer Note : WDTH and WDTL cannot be accessed by software.
Semiconductor Group
8-1
1997-10-01
Fail Safe Mechanisms C540U / C541U
8.1.1 Input Clock Selection The input clock rate of the watchdog timer is derived from the system clock of the C541U. There is a prescaler available, which is software selectable and defines the input clock rate. This prescaler is controlled by bit WDTPSEL in the SFR WDTREL. Tabel 8-1 shows resulting timeout periods at fOSC = 12 MHz. Special Function Register WDTREL (Address 86H) MSB Bit No. 7 86H WDT PSEL Reset Value : 00H LSB 0 WDTREL
6
5
4
3 Reload Value
2
1
Bit WDTPSEL
Function Watchdog timer prescaler select bit. If WDTPSEL=0, the watchdog timer is clocked by fOSC/12 (default after reset). If WDTPSEL=1, the watchdog timer is clocked by fOSC/192 Seven bit reload value for the high-byte of the watchdog timer. This value is loaded to WDTH when a refresh is triggered by a consecutive setting of bits WDT and SWDT.
WDTREL.6 - 0
Immediately after start, the watchdog timer is initialized to the reload value programmed to WDTREL.0-WDTREL.6. After an external hardware reset, an oscillator watchdog power on reset, or a watchdog timer reset, register WDTREL is cleared to 00H. The lower seven bits of WDTREL can be loaded by software at any time.
Table 8-1 Watchdog Timer Time-Out Periods (WDTPSEL = 0) WDTREL 00H 80H 7FH Time-Out Period fOSC = 12 MHz 32.768 ms 0.55 s 256 s Comments This is the default value Maximum time period Minimum time period
Semiconductor Group
8-2
1997-10-01
Fail Safe Mechanisms C540U / C541U
8.1.2 Watchdog Timer Control / Status Flags The watchdog timer is controlled by control and status flags which are located in SFR WDCON. Special Function Register WDCON (Address C0H) Bit No. MSB 7 C0H - Reset Value : XXXX 0000B LSB 0 SWDT WDCON
6 -
5 -
4 -
3 OWDS
2 WDTS
1 WDT
Bit - OWDS
Function Reserved bits for future use. Oscillator watchdog timer status flag. Set by hardware when an oscillator watchdog reset occured. Can be set and cleared by software. Watchdog timer status flag. Set by hardware when a watchdog timer reset occured. Can be cleared and set by software. Watchdog timer refresh flag. Set to initiate a refresh of the watchdog timer. Must be set directly before SWDT is set to prevent an unintentional refresh of the watchdog timer. Watchdog timer start flag. Set to activate the watchdog timer. When directly set after setting WDT, a watchdog timer refresh is performed.
WDTS
WDT
SWDT
Semiconductor Group
8-3
1997-10-01
Fail Safe Mechanisms C540U / C541U
8.1.3 Starting the Watchdog Timer The watchdog timer can be started by software (bit SWDT in SFR WDCON), but it cannot be stopped during active mode of the device. If the software fails to clear the watchdog timer an internal reset will be initiated. The reset cause (external reset or reset caused by the watchdog) can be examined by software (status flag WDTS in WDCON is set). A refresh of the watchdog timer is done by setting bits WDT (SFR WDCON) and SWDT consecutively. This double instruction sequence has been implemented to increase system security. It must be noted, however, that the watchdog timer is halted during the idle mode and power-down mode of the processor (see section "Power Saving Modes"). Therefore, it is possible to use the idle mode in combination with the watchdog timer function. But even the watchdog timer cannot reset the device when one of the power saving modes has been entered accidentally. 8.1.4 Refreshing the Watchdog Timer At the same time the watchdog timer is started, the 7-bit register WDTH is preset by the contents of WDTREL.0 to WDTREL.6. Once started the watchdog timer cannot be stopped by software but can be refreshed to the reload value only by first setting bit WDT (WDCON) and by the next instruction setting SWDT (WDCON). Bit WDT will automatically be cleared during the third machine cycle after having been set. This double-instruction refresh of the watchdog timer is implemented to minimize the chance of an unintentional reset of the watchdog unit. The reload register WDTREL can be written at any time, as already mentioned. Therefore, a periodical refresh of WDTREL can be added to the above mentioned starting procedure of the watchdog timer. Thus a wrong reload value caused by a possible distortion during the write operation to WDTREL can be corrected by software. Note : the watchdog timer registers WDTH and WDTL cannot be accessed by software. 8.1.5 Watchdog Reset and Watchdog Status Flag If the software fails to clear the watchdog in time, an internally generated watchdog reset is entered at the counter state 7FFCH. The duration of the reset signal then depends on the prescaler selection (either 8 or 128 machine cycles). This internal reset differs from an external one in so far as the watchdog timer is not disabled and bit WDTS is set. The WDTS is a flip-flop, which is set by a watchdog timer reset and can be cleared by an external hardware reset. Bit WDTS allows the software to examine from which source the reset was activated. The bit WDTS can also be cleared by software.
Semiconductor Group
8-4
1997-10-01
Fail Safe Mechanisms C540U / C541U
8.2
Oscillator Watchdog Unit
The oscillator watchdog unit serves for three functions: - Monitoring of the on-chip oscillator's function The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC oscillator and the device is brought into reset; if the failure condition disappears (i.e. the onchip oscillator has a higher frequency than the RC oscillator), the part executes a final reset phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog reset is released and the part starts program execution again. - Fast internal reset after power-on The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator has started. The oscillator watchdog unit also works identically to the monitoring function. - Control of external wake-up from software power-down mode (description see chapter 9) When the power-down mode is left by a low level at the INT0 pin or by the USB, the oscillator watchdog unit assures that the microcontroller resumes operation (execution of the powerdown wake-up interrupt) with the nominal clock rate. In the power-down mode the RC oscillator and the on-chip oscillator are stopped. Both oscillators are started again when power-down mode is released. When the on-chip oscillator has a higher frequency than the RC oscillator, the microcontroller starts operation after a final delay of typ. 1 ms in order to allow the on-chip oscillator to stabilize. Note: The oscillator watchdog unit is always enabled.
Semiconductor Group
8-5
1997-10-01
Fail Safe Mechanisms C540U / C541U
8.2.1 Functionality of the Oscillator Watchdog Unit Figure 8-2 shows the block diagram of the oscillator watchdog unit. It consists of an internal RC oscillator which provides the reference frequency for the comparison with the frequency of the onchip oscillator.
EWPD (PCON1.7) Activity on USB Bus P3.2 / INT0 Control Logic
WS (PCON1.4)
Power - Down Mode Activated Power-Down Mode Wake - Up Interrupt Control Logic Internal Reset
Start / Stop RC Oscillator
f RC
3 MHz Start / Stop
10
f1
Frequency Comparator
f 2 Delay
>1
XTAL1 XTAL2 On-Chip Oscillator
f2
WDCON (C0 H )
OWDS
Int. Clock
MCD03385
Figure 8-2 Functional Block Diagram of the Oscillator Watchdog The frequency coming from the RC oscillator is divided by 10 and compared to the on-chip oscillator's frequency. If the frequency coming from the on-chip oscillator is found lower than the frequency derived from the RC oscillator the watchdog detects a failure condition (the oscillation at the on-chip oscillator could stop because of crystal damage etc.). In this case it switches the input of the internal clock system to the output of the RC oscillator. This means that the part is being clocked even if the on-chip oscillator has stopped or has not yet started. At the same time the watchdog activates the internal reset in order to bring the C540U/C541U in its defined reset state. The reset is performed because a clock is available from the RC oscillator. This internal watchdog reset has the same effects as an externally applied reset signal with the following exceptions: The watchdog timer status flag WDTS is not reset (the watchdog timer however is stopped) and bit OWDS is set. This allows the software to examine error conditions detected by the watchdog timer even if meanwhile an oscillator failure occured.
Semiconductor Group
8-6
1997-10-01
Fail Safe Mechanisms C540U / C541U
The oscillator watchdog is able to detect a recovery of the on-chip oscillator after a failure. If the frequency derived from the on-chip oscillator is again higher than the reference the watchdog starts a final reset sequence which takes typ. 1 ms. Within that time the clock is still supplied by the RC oscillator and the part is held in reset. This allows a reliable stabilization of the on-chip oscillator. After that, the watchdog toggles the clock supply back to the on-chip oscillator and releases the reset request. If no reset is applied in this moment the part will start program execution. If an external reset is active, however, the device will keep the reset state until also the external reset request disappears. Furthermore, the status flag OWDS is set if the oscillator watchdog was active. The status flag can be evaluated by software to detect that a reset was caused by the oscillator watchdog. The flag OWDS can be set or cleared by software. An external reset request, however, also resets OWDS (and WDTS). 8.2.2 Fast Internal Reset after Power-On The C540U/C541U can use the oscillator watchdog unit for a fast internal reset procedure after power-on. Normally the members of the 8051 family (e. g. SAB 80C52) enter their default reset state not before the on-chip oscillator starts. The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state. Especially if a crystal is used the start up time of the oscillator is relatively long (typ. 1 ms). During this time period the pins have an undefined state which could have severe effects e.g. to actuators connected to port pins. In the C540U/C541U the oscillator watchdog unit avoids this situation. After power-on the oscillator watchdog's RC oscillator starts working within a very short start-up time (typ. less than 2 microseconds). In the following the watchdog circuitry detects a failure condition for the on-chip oscillator because this has not yet started (a failure is always recognized if the watchdog's RC oscillator runs faster than the on-chip oscillator). As long as this condition is valid the watchdog uses the RC oscillator output as clock source for the chip. This allows correct resetting of the part and brings all ports to the defined state. The delay time between power-on and correct reset state is max 34 s. More details about the fast internal reset procedure after power-on are described in chapter 5 of this manual.
Semiconductor Group
8-7
1997-10-01
Fail Safe Mechanisms C540U / C541U
Semiconductor Group
8-8
1997-10-01
Power Saving Modes C540U / C541U
9
Power Saving Modes
The C540U/C541U provides two power saving modes : - Idle mode - Power down mode. The functions of the power saving modes are controlled by bits which are located in the special function registers PCON und PCON1. PCON is located at address 87H. PCON1 is located in the mapped SFR area and is accessed with RMAP=1. Bit RMAP is located in SFR SYSCON (B1H) bit 4. The bits PDE, PDS and IDLE, IDLS located in SFR PCON select the power down mode or the idle mode, respectively. If the power down mode and the idle mode are set at the same time, powerdown takes precedence. Furthermore, register PCON contains two general purpose flags. For example, the flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred during normal operation or during an idle. Then an instruction that activates idle can also set one or both flag bits. When idle is terminated by an interrupt, the interrupt service routine can examine the flag bits.
Semiconductor Group
9-1
1997-10-01
Power Saving Modes C540U / C541U
Special Function Register PCON (Address 87H) Special Function Register PCON1 (Mapped Address 88H) Bit No. MSB 7 87H -
Reset Value : X00X0000B Reset Value : 0XX0XXXXB LSB 0 IDLE PCON
6 PDS
5 IDLS
4 -
3 GF1
2 GF0
1 PDE
88H
EWPD
-
-
WS
-
-
-
-
PCON1
The function of the shaded bit is not described in this section.
Symbol PDS
Function Power down start bit The instruction that sets the PDS flag bit is the last instruction before entering the power down mode Idle start bit The instruction that sets the IDLS flag bit is the last instruction before entering the idle mode. General purpose flag General purpose flag Power down enable bit When set, starting of the power down is enabled Idle mode enable bit When set, starting of the idle mode is enabled External wake-up from powe down enable bit Setting EWPD before entering power down mode, enables the external wakeup from power down mode capability via the pin P3.2/INT0 or by the USB module. Wake-up from software power down mode source select WS = 0 : wake-up via pin P3.2/INT0 selected (default after reset) WS = 1 : wake-up via USB bus selected Reserved bits for future use.
IDLS
GF1 GF0 PDE IDLE EWPD
WS
-
Semiconductor Group
9-2
1997-10-01
Power Saving Modes C540U / C541U
9.1
Idle Mode
In the idle mode the main oscillator of the C540U/C541U continues to run, but the CPU is gated off from the clock signal. However, the interrupt system, the SSC (C541U only), the USB module, and the timers with the exception of the watchdog timer (C541U only) are further provided with the clock. The CPU status is preserved in its entirety : the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle mode. The reduction of power consumption, which can be achieved by this feature depends on the number of peripherals running. If all peripherals are disabled or stopped, the maximum power reduction can be achieved. This state is also the test condition for the idle mode ICC. So the user has to take care which peripheral should continue to run and which has to be stopped during idle mode. Also the state of all port pins - either the pins controlled by their latches or controlled by their secondary functions - depends on the status of the controller when entering idle mode. Normally the port pins hold the logical state they had at the time idle mode was activated. If some pins are programmed to serve their alternate functions they still continue to output during idle mode if the assigned function is on. This applies to the serial interface in case it cannot finish reception or transmission during normal operation. The control signals ALE and PSEN hold at logic high levels. Table 9-1 Status of External Pins During Idle and Power-Down Mode Outputs Last Instruction Executed from Internal Code Memory Idle ALE PSEN Port 0 Port 2 Port 3 High High Data Data Data/alternate outputs Power-Down Low Low Data Data Data/last output Last Instruction Executed from External Code Memory Idle High High Float Address Data/alternate outputs Power-Down Low Low Float Data Data/last output
As in normal operation mode, the ports can be used as inputs during idle mode. Therefore, the timers can be used to count external events, and external interrupts will be detected. The idle mode is a useful feature which makes it possible to "freeze" the processor's status - either for a predefined time, or until an external event reverts the controller to normal operation, as discussed below. The watchdog timer is the only peripheral which is automatically stopped during idle mode.
Semiconductor Group
9-3
1997-10-01
Power Saving Modes C540U / C541U
9.1.1 Entering Idle Mode The idle mode is entered by two consecutive instructions. The first instruction sets the flag bit IDLE (PCON.0) and must not set bit IDLS (PCON.5), the following instruction sets the start bit IDLS (PCON.5) and must not set bit IDLE (PCON.0). The hardware ensures that a concurrent setting of both bits, IDLE and IDLS, does not initiate the idle mode. Bits IDLE and IDLS will automatically be cleared after being set. If one of these register bits is read the value that appears is 0. This double instruction is implemented to minimize the chance of an unintentional entering of the idle mode which would leave the watchdog timer's task of system protection without effect. PCON is not a bit-addressable register, so the above mentioned sequence for entering the idle mode is obtained by byte-handling instructions, as shown in the following example: ORL ORL PCON,#00000001B PCON,#00100000B ;Set bit IDLE, bit IDLS must not be set ;Set bit IDLS, bit IDLE must not be set
The instruction that sets bit IDLS is the last instruction executed before going into idle mode. In idle mode, the USB module can be fully functional or can be switched off. If it is switched off in idle mode the following steps must be processed before entering the idle mode : - USB module clock is switched off by software (resetting bit UCLK in SFR DCR) - additionally in full speed mode : USB PLL is switched off (resetting bit PCLK in SFR DCR)
9.1.2 Exit from Idle Mode There are two ways to terminate the idle mode: - The idle mode can be terminated by activating any enabled interrupt. This interrupt will be serviced and normally the instruction to be executed following the RETI instruction will be the one following the instruction that sets the bit IDLS. - The other way to terminate the idle mode, is a hardware reset. Since the oscillator is still running, the hardware reset must be held active only for two machine cycles for a complete reset. After leaving the idle mode through e.g. an interrupt with a switched-off USB module, a well defined procedure must be executed foragain switching on the USB module : - in full speed mode only USB PLL is switched on (setting bit PCLK in SFR DCR) and waiting 3 ms for PLL being locked - USB module clock is switched on (setting bit UCLK in SFR DCR) This switch off/on procedure assures a proper operation of the USB clock system. If the idle mode is terminated by a hardware reset, the USB module has to be reconfigured as defined for the hardware reset case.
Semiconductor Group
9-4
1997-10-01
Power Saving Modes C540U / C541U
9.2
Power Down Mode
In the power down mode, the RC osciillator and the on-chip oscillator which operates with the XTAL pins is stopped. Therefore, all functions of the microcontroller are stopped and only the contents of the on-chip RAM, XRAM and the SFR's are maintained. The port pins, which are controlled by their port latches, output the values that are held by their SFR's. The port pins which serve the alternate output functions show the values they had at the end of the last cycle of the instruction which initiated the power down mode. ALE and PSEN hold at logic low level (see table 9-1). The power down mode can be left either by an active reset signal or by a low signal at the P3.2/INT0 pin or any activity on the USB bus. The USB module enters the suspend state when it detects no activity on the USB bus for more than 6 ms. The suspend state is left when bus activity is detected on the USB bus. Leaving the suspend state can (if selected and enabled) wake-up the power down mode. Using reset to leave power down mode puts the microcontroller with its SFRs into the reset state. Using the INT0 pin or USB bus for power down mode exit maintains the state of the SFRs, which has been frozen when power down mode is entered. In the power down mode of operation, VCC can be reduced to minimize power consumption. It must be ensured, however, that is VCC not reduced before the power down mode is invoked, and that VCC is restored to its normal operating level before the power down mode is terminated.
Semiconductor Group
9-5
1997-10-01
Power Saving Modes C540U / C541U
9.2.1 Entering Power Down Mode The power down mode is entered by two consecutive instructions. The first instruction has to set the flag bit PDE (PCON.1) and must not set bit PDS (PCON.6), the following instruction has to set the start bit PDS (PCON.6) and must not set bit PDE (PCON.1). The hardware ensures that a concurrent setting of both bits, PDE and PDS, does not initiate the power down mode. Bits PDE and PDS will automatically be cleared after having been set and the value shown by reading one of these bits is always 0. This double instruction is implemented to minimize the chance of unintentionally entering the power down mode which could possibly "freeze" the chip's activity in an undesired status. Important : the USB module must be switched off from the system clock prior to enabling the power down mode by software : PCON is not a bit-addressable register, so the above mentioned sequence for entering the powerdown mode is obtained by byte-handling instructions, as shown in the following example: ANL ANL ORL ORL DCR,#11111101B DCR,#11111110B PCON,#00000010B PCON,#01000000B ;clear bit UCLK; USB clock is switched off ;clear bit PCLK, stop PLL (required only in full speed mode) ;set bit PDE, bit PDS must not be set ;set bit PDS, bit PDE must not be set, enter power-down
The instruction that sets bit PDS is the last instruction executed before going into power down mode. When the double instruction sequence shown above is used and when bit EWPD in SFR PCON1 is 0, the power down mode can only be left by a reset operation. If the wake-up from power down capability is required, its function must be enabled prior to executing the double instruction sequence shown above. ORL ORL SYSCON,#00010000B PCON1,#80H ;set RMAP ;enable wake-up from power-down by setting EWPD ;80H = wake-up through pin P3.2/INT0 ;90H = wake-up through USB bus ;reset RMAP (for future SFR accesses)
ANL
SYSCON,#11101111B
Note :Before entering the power down mode, the port latch of SFR P3.2 (P3.2/INT0 pin) should contain a "1" (pin operates as input). Otherwise, the wake-up sequence discussed in the next chapter will be started immediately when power down mode is entered. If the wake-up from software power down mode through USB bus capability is selected, the USB receiver must be enabled in order to detect any activity on the USB bus lines. Therefore, bit RPWD in the USB device power down register DPWDR must be cleared before enering software power down mode. The USB module enters the suspend state when it detects no activity on teh USB bus for more than 6 ms.
Semiconductor Group
9-6
1997-10-01
Power Saving Modes C540U / C541U
9.2.2 Exit from Power Down Mode If the power down mode is exit via a hardware reset, the microcontroller with its SFRs is put into the hardware reset state and the content of RAM and XRAM are not changed. The reset signal that terminates the power down mode also restarts the RC oscillator and the on-chip oscillatror. The reset operation should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (similar to power-on reset). The USB clock system must be cotrolled as described for the hardware reset in chapter 5. Figure 9-1 shows the procedure which must is executed when the power down mode is left via the wake-up capability.
Power Down Mode 1) P3.2 / INT0 or Activity Detected on USB Bus
Latch Phase 2)
Watchdog Circuit Oscillator Start-Up Phase 3)
Execution of Interrupt at 007B H 4) 5)
min. 10 s
typ. 5 ms RETI Instruction
Detailed Timing of Beginning of Phase 4 ALE
PSEN
P2
Invalid Address
00H
P0
Invalid Address / Data
7BH 1st Instr. of ISR
MCT03418
Figure 9-1 Wake-up from Power Down Mode Procedure
Semiconductor Group
9-7
1997-10-01
Power Saving Modes C540U / C541U
When the power-down mode wake-up capability has been enabled (bit EWPD in SFR PCON1 set) prior to entering power down mode, the power down mode can be exit either via P3.2/INT0 or an activity on the USB bus. 9.2.2.1 Exit via Pin P3.2/INT0
The following procedure : 1. In power down mode pin INT0 must be held at high level. 2. Power down mode is left when INT0 goes low. With INT0 = low the internal RC oscillator is started. INT0 is then latched by the RC oscillator clock signal. Therefore, INT0 should be held at low level for at least 10 s (latch phase). After this delay INT0 can be set again to high level if required. Thereafter, the oscillator watchdog unit controls the wake-up procedure in its start-up phase. 3. The oscillator watchdog unit starts its operation. When the on-chip oscillator clock is detected for stable nominal frequency, the microcontroller further waits for a delay of typically 5 ms and then starts again with its operation initiating the power down wake-up interrupt. The interrupt address of the first instruction to be executed after wake-up is 007BH. 4. The clock system of the USB module must be setup again by software : USB PLL is switched on by setting bit PCLK in SFR DCR.(only required in full speed mode); Therafter, the PLL must be stabilized by waiting typically 3 ms. Now bit UCLK in SFR DCR can be set. 5. After the RETI instruction of the power down wake-up interrupt routine has been executed, the instruction which follows the initiating power down mode double instruction sequence will be executed. The peripheral units timer 0/1, SSC, and WDT are frozen until end of phase 4. All interrupts of the C541U are disabled from phase 2) until the end of phase 4). Other Interrupts can be first handled after the RETI instruction of the wake-up interrupt routine. Depending on the requirements, point 4 can also be executed in pahse 5) after the execution of the RETI instruction described in point 5 above. 9.2.2.2 Exit via UBS Bus
If the wake-up from software power down mode through USB bus capability has been selected, any activity on the USB bus causes the termination of the suspend state, triggers the watchdog unit and starts the wake-up procedure. After the start trigger by the USB bus activity, the actions 3. to 5. as described above are executed. The wake-up trigger signal from the USB module can only be generated if the USB receiver circuitry was enabled in software power down mode.
Semiconductor Group
9-8
1997-10-01
OTP Memory Operation C540U / C541U
10
OTP Memory Operation
The C541U contains a 8k byte one-time programmable (OTP) program memory (C540U : 4k byte). With the C540U/C541U fast programming cycles are achieved (1 byte in 100 sec). Also several levels of OTP memory protection can be selected. This chapter describes in detail the C540U/C541U programmimg interface. 10.1 Programming Configuration
For programming of the device, the C540U/C541U must be put into the programming mode. This typically is done not in-system but in a special programming hardware. In the programming mode the C540U/C541U operates as a slave device similar as an EPROM standalone memory device and must be controlled with address/data information, control lines, and an external 11.5V programming voltage. In the programming mode port 0 provides the bidirectional data lines and port 2 is used for the multiplexed address inputs. The upper address information at port 2 is latched with the signal PALE. For basic programming mode selection the inputs RESET, PSEN, EA/VPP, ALE, PMSEL1/0, and PSEL are used. Further, the inputs PMSEL1,0 are required to select the access types (e.g. program/verify data, write lock bits, ....) in the programming mode. In programming mode VCC/VSS and a clock signal at the XTAL pins must be applied to the C541U. The 11.5V external programming voltage is input through the EA/VPP pin. Figure 10-2 shows the pins of the C540U/C541U which are required for controlling of the OTP programming mode.
V CC
V SS
A0 - A7 / A8 - A12 PALE PMSEL0 PMSEL1
Port 2
Port 0
D0 - D7
EA / V PP
C540U C541U
PROG PRD RESET
XTAL1 XTAL2
PSEN PSEL
MCS03386
Figure 10-2 C540U/C541U Programming Mode Configuration
Semiconductor Group
10-1
1997-10-01
OTP Memory Operation C540U / C541U
10.2
Pin Configuration
Figure 10-3 shows the detailed P-LCC-44 pin configuration of the C540U/C541U in programming mode. Figure 10-4 shows the detailed P-SDIP-52 pin configuration.
N.C. N.C. N.C. N.C. N.C. N.C. N.C. D0 D1 D2 D3
6 5 4 3 2 1 44 43 42 41 40 N.C. V CC V SS RESET PMSEL0 N.C: PMSEL1 PSEL PRD PALE GND 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 D4 D5 D6 D7 EA / V PP N.C. PROG PSEN A7 A6 A5
C540U C541U Programming Mode
18 19 20 21 22 23 24 25 26 27 28
A0 / A8 A1 / A9 A2 / A10 A3 / A11 A4 / A12 GND GND XTAL2 XTAL1 V SS V CC
MCP03387
Figure 10-3 P-LCC-44 Pin Configuration of the C540U/C541U in Programming Mode (top view)
Semiconductor Group
10-2
1997-10-01
OTP Memory Operation C540U / C541U
N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. V CC V SS RESET PMSEL0 N.C. N.C. PMSEL1 PSEL PRD PALE GND GND GND XTAL2 XTAL1 V SS V CC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
C540U C541U Programming Mode
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
N.C. P1.5 / SLS D0 D1 D2 D3 D4 D5 D6 D7 EA / V PP N.C. N.C. PROG PSEN N.C. N.C. A7 A6 A5 A4 / A12 A3 / A11 A2 / A10 A1 / A9 A0 / A8 N.C.
MCP03388
Figure 10-4 P-SDIP-52 Pin Configuration of the C540U/C541U in Programming Mode (top view)
Semiconductor Group
10-3
1997-10-01
OTP Memory Operation C540U / C541U
10.3
Pin Definitions
The following table 10-2 contains the functional description of all C540U/C541U pins which are required for OTP memory programming Table 10-2 Pin Definitions and Functions in Programming Mode Symbol RESET 10 Pin Numbers P-LCC-44 P-SDIP-52 12 I Reset This input must be at static "1" (active) level during the whole programming mode. Programming mode selection pins These pins are used to select the different access modes in programming mode. PMSEL1,0 must satisfy a setup time to the rising edge of PALE. When the logic level of PMSEL1,0 is changed, PALE must be at low level. PMSEL PMSEL Access Mode 1 0 0 0 1 1 PSEL 14 17 I 0 1 0 1 Reserved Read version bytes Program/read lock bits Program/read OTP memory byte I/O*) Function
PMSEL0 PMSEL1
11 13
13 16
I I
Basic programming mode select This input is used for the basic programming mode selection and must be switched according figure 105. Programming mode read strobe This input is used for read access control for OTP memory read, version byte read, and lock bit read operations. Programming mode address latch enable PALE is used to latch the high address lines. The high address lines must satisfy a setup and hold time to/ from the falling edge of PALE. PALE must be at low level whenever the logic level of PMSEL1,0 is changed. XTAL2 Output of the inverting oscillator amplifier.
PRD
15
18
I
PALE
16
19
I
XTAL2
20
23
O
*) I = Input O = Output
Semiconductor Group
10-4
1997-10-01
OTP Memory Operation C540U / C541U
Table 10-2 Pin Definitions and Functions in Programming Mode (cont'd) Symbol XTAL1 A0/A8 A7 21 24 - 31 Pin Numbers P-LCC-44 P-SDIP-52 24 28 - 35 I I XTAL1 Input to the oscillator amplifier. Address lines P2.0-7 are used as multiplexed address input lines A0-A7 and A8-A12. A8-A12 must be latched with PALE. Address A12 is requred only for the C541U. Program store enable This input must be at static "0" level during the whole programming mode. Programming mode write strobe This input is used in programming mode as a write strobe for OTP memory program and lock bit write operations During basic programming mode selection a low level must be applied to PROG. External Access / Programming voltage This pin must be at 11.5 V (VPP) voltage level during programming of an OTP memory byte or lock bit. During an OTP memory read operation this pin must be at high level (VIH). This pin is also used for basic programming mode selection. At basic programming mode selection a low level must be applied to EA/VPP. Data lines 0-7 During programming mode, data bytes are read or written from or to the C540U/C541U via the bidirectional D0-7 lines which are located at port 0. Circuit ground potential must be applied to these pins in programming mode. Power supply terminal must be applied to these pins in programming mode. Not Connected These pins should not be connected in programming mode. Ground pins In programming mode these pins must be connected to VIL level. I/O*) Function
PSEN
32
38
I
PROG
33
39
I
EA/VPP
35
42
I
D0 - 7
43 - 38
50 - 43
I/O
VSS VCC
N.C.
9, 22 8, 23 1, 12,, 34, 44
11, 25 10, 26 1 - 9, 14, 15, 27, 36, 37, 40, 41, 52 20 - 22
- - -
GND
17 - 19
I
*) I = Input O = Output
Semiconductor Group
10-5
1997-10-01
OTP Memory Operation C540U / C541U
10.4
Programming Mode Selection
The selection for the OTP programming mode can be separated into two different parts : - Basic programming mode selection - Access mode selection With the basic programming mode selection the device is put into the mode in which it is possible to access the OTP memory through the programming interface logic. Further, after selection of the basic programming mode, OTP memory accesses are executed by using one of the access modes. These access modes are OTP memory byte program/read, version byte read, and program/read lock byte operations. 10.4.1 Basic Programming Mode Selection The basic programming mode selection scheme is shown in figure 10-5.
V CC
Clock (XTAL1 / XTAL2) RESET PSEN PMSEL1,0 PROG PRD PSEL PALE "0" "0" "1" 0,1 Stable "1" "0"
5V
V PP
EA / V PP During this Period Signals are not actively driven 0V
V IH1
Ready for Access Mode Selection
MCT03389
Figure 10-5 Basic Programming Mode Selection
Semiconductor Group
10-6
1997-10-01
OTP Memory Operation C540U / C541U
The basic programming mode is selected by executing the following steps : - With a stable Vcc a clock signal is applied to the XTAL pins; the RESET pin is set to "1" level and the PSEN pin is set to "0" level. - PROG, PALE, PMSEL1 and EA/VPP are set to "0" level; PRD, PSEL, and PMSEL0 are set to "1" level. - PSEL is set to from "1" to "0" level and thereafter PROG is switched to "1" level. - PMSEL1,0 can now be changed; after EA/VPP has been set to VIH high level or to VPP the OTP memory is ready for access. The pins RESET and PSEN must stay at "1" respectively "0" static signal level during the whole programming mode. With a falling edge of PSEL the logic state of ALE/PROG and VPP(EA) is internally latched. These two signals are now used as programming write pulse signal (PROG) and as programming voltage input pin VPP. After the falling edge of PSEL, PSEL must stay at "0" state during all programming operations. Note: If protection level 1 to 3 has been programmed (see section 10.6) and the programming mode has been left, it is no more possible to enter the programming mode ! 10.4.2 OTP Memory Access Mode Selection When the C540U/C541U has been put into the programming mode using the basic programming mode selection, several access modes of the OTP memory programming interface are available. The conditions for the different control signals of these access modes are listed in table 10-3. Table 10-3 Access Modes Selection Access Mode Program OTP memory byte Read OTP memory byte Program OTP lock bits Read OTP lock bits Read OTP version byte EA/ VPP VPP VIH VPP VIH VIH H H L H Byte addr. of sign. byte H H H L PROG PRD H PMSEL 1 H 0 H Address (Port 2) A0-7 A8-15 - Data (Port 0) D0-7 D1,D0 see table 4 D0-7
The access modes from the table above are basically selected by setting the two PMSEL1,0 lines to the required logic level. The PROG and PRD signal are the write and read strobe signal. Data is transfered via port 0 and addresses are applied to port 2. The following sections describes the details of the different access modes.
Semiconductor Group
10-7
1997-10-01
OTP Memory Operation C540U / C541U
10.5
Program / Read OTP Memory Bytes
The program/read OTP memory byte access mode is defined by PMSEL1,0 = 1,1. It is initiated when the PMSEL1,0 = 1,1 is valid at the rising edge of PALE. With the falling edge of PALE the upper addresses A8-A12 of the 13-bit OTP memory address are latched. After A8-A12 has been latched, A0-A7 is put on the address bus (port 2). A0-A7 must be stable when PROG is low or PRD is low. If subsequent OTP address locations are accessed with constant address information at the high address lines A8-12, A8-A12 must only be latched once (page address mechanism). Figure 10-6 shows a typical OTP memory programming cycle with a following OTP memory read operation. In this example A0-A12 of the read operation are identical to A8-A12 of the preceeding programming operation. For the C540U address line A12 is not required.
PMSEL1,0 Port 2 PALE Port 0 A8-A12
1,1 A0-A7
D0 - D7 min. 100 s
D0 - D7
PROG
min. 100 ns
PRD
MCT03419
Figure 10-6 C541U Programming / VerifyOTP Memory Access Waveform If the address lines A8-A12 must be updated, PALE must be activated for the latching of the new A8-A12 value. Control, address, and data information must only be switched when the PROG and PRD signals are at high level. The PALE high pulse must always be executed if a different access mode has been used prior to the actual access mode.
Semiconductor Group
10-8
1997-10-01
OTP Memory Operation C540U / C541U
Figure 10-7 shows a waveform example of the program/read mode access for several OTP memory bytes. In this example OTP memory locations 3FDH to 400H are programmed. Thereafter, OTP memory locations 400H and 3FDH are read.
PMSEL1,0 PALE 3FD Port 2 Port 0 PROG PRD 03 FD Data 1 3FE FE Data 2 3FF FF Data 3
1,1
400 04 00 Data 4
400 00 Data 4 03
3FD FD Data 1
MCT03420
Figure 10-7 Typical OTP Memory Programming/Verify Access Waveform
Semiconductor Group
10-9
1997-10-01
OTP Memory Operation C540U / C541U
10.6
Lock Bits Programming / Read
The C540U/C541U has two programmable lock bits which, when programmed according tabie 104, provide four levels of protection for the on-chip OTP code memory. The state of the lock bits can also be read. Table 10-4 Lock Bit Protection Types Lock Bits at D1,D0 D1 1 D0 1 Protection Protection Type Level Level 0 The OTP lock feature is disabled. During normal operation of the C540U/C541U, the state of the EA pin is not latched on reset. During normal operation of the C540U/C541U, MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory. EA is sampled and latched on reset.An OTP memory read operation is only possible using the OTP verification mode for protection level 1. Further programming of the OTP memory is disabled (reprogramming security). Same as level 1, but also OTP memory read operation using OTP verification mode is disabled. Same as level 2; but additionally external code execution by setting EA=low during normal operation of the C540U/C541U is no more possible. External code execution, which is initiated by an internal program (e.g. by an internal jump instruction above the ROM boundary), is still possible.
1
0
Level 1
0 0
1 0
Level 2 Level 3
Note : A 1 means that the lock bit is unprogrammed. 0 means that lock bit is programmed. For a OTP verify operation at protection level 1, the C540U/C541U must be put into the OTP verification mode 2. If a device is programmed with protection level 2 or 3, it is no more possible to verify the OTP content of a customer rejected (FAR) OTP device. When a protection level has been activated by programming of the lock bits, the basic programming mode must be left for activation of the protection mechanisms. This means, after the activation of a protection level further OTP program/veriry operations are still possible if the basic programming mode is maintained. The state of the lock bits can always be read if protection level 0 is selected. If protection level 1 to 3 has been programmed and the programming mode has been left, it is no more possible to enter the programming mode: In this case, also the lock bits cannot be read anymore. Figure 10-8 shows the waveform of a lock bit write/read access. For a simple drawing, the PROG pulse is shortened. In reality, for Lock Bit programming, a 100s PROG low puls must be applied.
Semiconductor Group
10-10
1997-10-01
OTP Memory Operation C540U / C541U
PMSEL1,0 PALE Port 0 (D1, D0) PROG PRD 1,0
1,0
1,0
MCT03421
The example shows the programming and reading of a protection level 1.
Figure 10-8 Write/Read Lock Bit Waveform
Semiconductor Group
10-11
1997-10-01
OTP Memory Operation C540U / C541U
10.7
Access of Version Bytes
The C540U/C541U provides three version bytes at address locations FCH, FDH, and FEH. The information stored in the version bytes, is defined by the mask of each microcontroller step, Therefore, the version bytes can be read but not written. The three version bytes hold information as manufacturer code, device type, and stepping code. For reading of the version bytes the control lines must be used according table 10-3 and figure 109. The address of the version byte must be applied at the port 1 address lines. PALE must not be activated.
PMSEL1,0 PALE Port 2 Port 0 PROG PRD FC Ver. 0
0,1
FD Ver. 1
FE Ver. 2
MCT03422
Figure 10-9 Read Version Byte(s) Waveform Version bytes are typically used by programming systems for adapting the programming firmware to specifc device characteristics such as OTP size etc. Note: The 3 version bytes are implemented in a way that they can be also read during normal program execution mode as a mapped register with bit RMAP in SFR SYSCON set. The addresses of the version bytes in normal mode and programming mode are identical and therefore they are located in the SFR address range. The first step of the C540U/C541U will contain the following information at the version bytes : Name Version Byte 0 Version Byte 1 Version Byte 2 Address FCH FDH FEH Value C5H C1H 01H
Future steppings of the C540U/C541U will have a different version byte 2 (incremented value. version bytes 0 and 1 will remain unchanged for future steppings of the C540U/C541U.
Semiconductor Group
10-12
1997-10-01
OTP Memory Operation C540U / C541U
10.8
OTP Verify with Protection Level 1
If the C540U/C541U OTP program memory is protected in protection level 1), an OTP verification as shown in figure 10-10 is used to verify the content of the OTP. The detailed timing characteristics of this OTP verification mode is shown in the AC specifications (chapter 11).
RESET 6 CLP 1. ALE pulse after reset ALE Latch Port 0 Data for Addr. 0 Latch
Data for Addr. 1 Data for Ad. X 16 - 1
3 CLP
Latch
Data for Addr. X 16
Latch
Data for Addr. X 16 + 1
P3.5 Inputs : ALE = V SS PSEN, EA = V IH RESET =
Low: Verify Error High: Verify ok
MCT03289
Figure 10-10 OTP Verification Mode Timing The OTP verification mode is selected when the inputs PSEN, EA, and ALE are put to the specified logic levels. With RESET going inactive, the OTP verification mode sequence is started. The C541U outputs an ALE signal with a period of 3 CLPand expects data bytes at port 0. The data bytes at port 0 are assigned to the OTP addresses in the following way: 1. Data Byte = 2. Data Byte = 3. Data Byte = : 16. Data Byte = : content of internal OTP address 0000H content of internal OTP address 0001H content of internal OTP address 0002H content of internal OTP address 000FH
The C540U/C541U does not output any address information during the OTP verification mode. The first data byte to be verified is always the byte which is assigned to the internal OTP address 0000H and must be put onto the data bus with the first ALE pulse after the falling edge of RESET. With each following ALE pulse the ROM address pointer is internally incremented and the expected data byte for the next OTP address must be delivered externally. Between two ALE pulses the data at port 0 is latched (at 3 CLP after ALE rising edge) and compared internally with the OTP content of the actual address. If an verify error is detected, the error
Semiconductor Group
10-13
1997-10-01
OTP Memory Operation C540U / C541U
condition is stored internally. After each 16th data byte the cumulated verify result (pass or fail) of the last 16 verify operations is output at P3.5. This means that P3.5 stays at static level (low for fail and high for pass) during the time when the following 16 bytes are checked. In OTP verification mode, the C540U/C541U must be provided with a system clock at the XTAL pins. Figure 10-11 shows an application example of a external circuitry which allows to verify a protected OTP inside the. With RESET going inactive, the C540U/C541U starts the OTP verify sequence. Its ALE is clocking an 14-bit address counter. This counter generates the addresses for an external EPROM which is programmed with the content of the internal (protected) OTP. The verify detect logic typically displays the state of the verify error output P3.5. P3.5 can be latched with the falling edge of ALE. When the last byte of the internal OTP has been handled, the C540U/C541U starts generating a PSEN signal. This signal or the CY signal of the address counter indicate to the verify detect logic the end of the internal OTP verification.
P3.5
Verify Detect Logic CY CLK 2K 12 / 13 - Bit Address Counter R A0 - A12 or A0 - A11
ALE
C540U C541U
&
Compare Code ROM
V CC
& RESET Port 0 D0 - D7
V CC
EA P2.7 PSEN CS OE
MCS03423
Figure 10-11 OTP Verification with Protection Level 1 - External Circuitry Example
Semiconductor Group
10-14
1997-10-01
Device Specifications C540U / C541U
11
Device Specifications
Advance Information 11.1 Absolute Maximum Ratings Ambient temperature under bias (TA) .............................................................. 0 C to + 70 C Storage temperature (TST) ...............................................................................- 65 C to + 150 C Voltage on VCC pins with respect to ground (VSS) ............................................- 0.5 V to 6.5 V Voltage on any pin with respect to ground (VSS) ..............................................- 0.5 V to VCC + 0.5 V Input current on any pin during overload condition..........................................- 10 mA to + 10 mA Absolute sum of all input currents during overload condition ..........................| 100 mA | Power dissipation.............................................................................................TBD
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the Voltage on VCC pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings.
Semiconductor Group
11-1
1997-10-01
Device Specifications C540U / C541U
11.2 DC Characteristics
VCC = 4.0V to 5.5V (5V +10%, -20%); VSS = 0 V
Parameter Input low voltage (except EA, RESET) Input low voltage (EA) Input low voltage (RESET) Symbol min.
TA = 0 to 70 C
Limit Values max. 0.2 VCC - 0.1 0.2 VCC - 0.3 0.2 VCC + 0.1 V V V V V V V V V V V A A A pF mA - - - - - - - 0.5 - 0.5 - 0.5 0.2 VCC + 0.9 0.7 VCC 0.6 VCC - - - 2.4 0.9 VCC 2.4 0.9 VCC - 10 - 65 - - - 10.9 Unit Test Condition
VIL VIL1 VIL2
Input high voltage (except XTAL1, VIH RESET) Input high voltage to XTAL1 Input high voltage to RESET Output low voltage Ports 1, 2, 3 P1.0, P1.1, P3.0 Output low voltage (port 0, ALE, PSEN)
VCC + 0.5 VCC + 0.5 VCC + 0.5
0.45 0.45 0.45 - - - - - 50 - 650 1 10
VIH1 VIH2 VOL VOL1
IOL = 1.6 mA 1) IOL = 10 mA 1) IOL = 3.2 mA 1) IOH = - 80 A, IOH = - 10 A IOH = - 800 A IOH = - 80 A 2) VIN = 0.45 V VIN = 2 V
0.45 < VIN < VCC
Output high voltage (ports 1, 2, 3) VOH Output high voltage (port 0 in external bus mode, ALE, PSEN) Logical 1-to-0 transition current (ports 1, 2, 3) Input leakage current (port 0, EA) Pin capacitance Overload current Programming voltage Notes see next page
VOH2
Logic 0 input current (ports 1, 2, 3) IIL
ITL ILI CIO IOV VPP
fc = 1 MHz, TA = 25 C 7)
6) 7)
5
12.1
V
11.5 V 5%
Semiconductor Group
11-2
1997-10-01
Device Specifications C540U / C541U
Power Supply Current Parameter Active mode Idle mode Power-down mode
Notes : 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VCC specification when the address lines are stabilizing. 3) IPD (power-down mode) is measured under following conditions: EA = Port 0 = VCC ; XTAL2 = N.C.; XTAL1 = VSS ; RESET = VSS; all other pins are disconnected. the USB transceiver is switched off; 4) ICC (active mode) is measured with: XTAL1 driven with tCLCH , tCHCL = 5 ns , VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL2 = N.C.; EA = RESET = Port 0 = Port 1 = VCC ; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (appr. 1 mA). 5) ICC (idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tCLCH , tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL2 = N.C.; EA = RESET = Vss ; Port 0 = VCC ; all other pins are disconnected; 6) Overload conditions occur if the standard operating conditions are exceeded, ie. the voltage on any pin exceeds the specified range (i.e. VOV > VCC + 0.5 V or VOV < VSS - 0.5 V). The supply voltage VCC and VSS must remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA. 7) Not 100% tested, guaranteed by design characterization. 8) The typical ICC values are periodically measured at TA = +25 C but not 100% tested. 9) The maximum ICC values are measured under worst case conditions (TA = 0 C and VCC = 5.5 V)
Symbol 12 MHz 12 MHz
Limit Values typ. 8) max. 9) TBD TBD 50 15 TBD TBD
Unit Test Condition mA mA A
4) 5)
ICC ICC IPD
VCC = 2...5.5 V 3)
Semiconductor Group
11-3
1997-10-01
Device Specifications C540U / C541U
11.3 AC Characteristics
VCC = 4.0V to 5.5V (5V +10%, -20%); VSS = 0 V
Program Memory Characteristics Parameter Symbol
TA = 0 to 70 C
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Limit Values 10-MHz clock Duty Cycle 0.4 to 0.6 min. max. - - - 80 - - 51 - 23 - 140 Variable Clock 1/CLP = 2 MHz to 12 MHz **) min. CLP - 40 max. -
Unit
ALE pulse width Address setup to ALE Address hold after ALE ALE to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN
*)
tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ *) tPXAV tAVIV tAZPL
*)
43 13 13 - 13 86 - 0 - 28 - 0
ns ns ns ns ns ns
TCLHmin -20 - TCLHmin -20 - - 2 CLP - 87 TCLLmin -20 - CLP+ - TCLHmin -30 - 0 - TCLLmin - 5 - 0
CLP+ ns TCLHmin- 65 - - ns ns TCLLmin -10 ns 2 CLP + ns TCLHmin -60 - ns
Interfacing the C540U/C541U to devices with float times up to 28 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. For correct function of the USB module the C540U/C541U must operate with 12 MHz external clock. The microcontroller (except the USB module) operates down to 2 MHz.
**)
Semiconductor Group
11-4
1997-10-01
Device Specifications C540U / C541U
AC Characteristics (cont'd) External Data Memory Characteristics Parameter Symbol 10-MHz clock Duty Cycle 0.4 to 0.6 min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD max. - - - 110 Limit Values Variable Clock 1/CLP= 2 MHz to 12 MHz Unit
min. 3 CLP - 70 3 CLP - 70 CLP - 27 - 0
max. - - - 2 CLP+ TCLHmin - 90 - CLP - 20 4 CLP - 133 4 CLP + TCLHmin -155 CLP+ TCLLmin+ 50 - TCLHmin + 25 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ
180 180 56 - 0 - - - 66 70 8 8 163 8 -
63 200 211 166 - 58 - - - 0
- - - CLP + TCLLmin - 50 2 CLP - 97 TCLHmin - 25 TCLLmin - 25
3 CLP + - TCLLmin - 120 TCLHmin - 25 - - 0
Semiconductor Group
11-5
1997-10-01
Device Specifications C540U / C541U
External Clock Drive Characteristics Parameter Symbol CPU Clock = 12 MHz Duty cycle 0.4 to 0.6 min. Oscillator period High time Low time Rise time Fall time Oscillator duty cycle Clock cycle CLP TCLH TCLL 83.3 33 33 - - 0.4 33 max. 83.3 - - 12 12 0.6 50 Variable CPU Clock 1/CLP = 2 to 12 MHz min. 83.3 33 33 - - 33 / CLP CLP * DCmin max. 500 CLP-TCLL CLP-TCLH 12 12 1 - 33 / CLP ns ns ns ns ns - Unit
tR tF
DC TCL
CLP * DCmax ns
SSC Interface Characteristics Parameter Clock Cycle Time : Master Mode Slave Mode Clock high time Clock low time Data output delay Data output hold Data input setup Data input hold TC bit set delay SLS low to first SCLK clock edge SLS low to STO active SLS high to STO tristate Data output delay (already defined) Symbol min. Limit Values max. - - - - 100 - - - 8 CLP - - 100 100 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 667 667 300 300 - 0 100 50 - 2 tCLCL Unit
tSCLK tSCLK tSCH tSCL tD tHO tS tHI tDTC tSC tTS tST tD
Last SCLK clock edge to SLS high tCS
tCLCL
0 - -
Semiconductor Group
11-6
1997-10-01
Device Specifications C540U / C541U
t LHLL
ALE
t AVLL t
LLIV
t PLPH t LLPL t PLIV
PSEN
t AZPL t LLAX
t PXAV t PXIZ t PXIX
Port 0
A0 - A7
Instr.IN
A0 - A7
t AVIV
Port 2
A8 - A15
A8 - A15
MCT00096
Figure 11-12 Program Memory Read Cycle
Semiconductor Group
11-7
1997-10-01
Device Specifications C540U / C541U
t WHLH
ALE
PSEN
t LLDV t LLWL
RD
t RLRH
t RLDV t AVLL t LLAX2 t RLAZ
Port 0 A0 - A7 from Ri or DPL Data IN
t RHDZ t RHDX
A0 - A7 from PCL Instr. IN
t AVWL t AVDV
Port 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
MCT00097
Figure 11-13 Data Memory Read Cycle
Semiconductor Group
11-8
1997-10-01
Device Specifications C540U / C541U
t WHLH
ALE
PSEN
t LLWL
WR
t WLWH
t QVWX t AVLL t LLAX2
A0 - A7 from Ri or DPL
t WHQX t QVWH
Data OUT A0 - A7 from PCL Instr.IN
Port 0
t AVWL
Port 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH
MCT00098
Figure 11-14 Data Memory Write Cycle
TCL H
tR
tF
XTAL1
TCL L CLP
0.7 V CC 0.2 V CC - 0.1
MCT03310
Figure 11-15 External Clock Drive on XTAL1
Semiconductor Group
11-9
1997-10-01
Device Specifications C540U / C541U
t SCLK t SCL
SCLK
t SCH
tD
STO MSB
t HD
~ ~
LSB
tS
SRI
t HI
MSB
~ ~
~ ~
~ ~
LSB
~ ~
t DTC
TC
~ ~
MCT02417
Notes :
Shown is the data/clock relationship for CPOL=CPHA=1. The timing diagram is valid for the other cases accordingly. In the case of slave mode and CPHA=0, the output delay for the MSB applies to the falling edge of SLS (if transmitter is enabled). In the case of master mode and CPHA=0, the MSB becomes valid after the data has been written into the shift register, i.e. at least one half SCLK clock cycle before the first clock transition.
Figure 11-16 SSC Master Mode Timing
Semiconductor Group
11-10
1997-10-01
Device Specifications C540U / C541U
t SCLK
t SCH
t SCL
SCLK (CPOL = 1)
SCLK (CPOL = 0)
t SC
SLS
t CS t ST
t TS
STO (CPHA = 0) DOUT 7
tD
tD
DOUT 0
tD
tD
STO (CPHA = 1) DOUT 7 DOUT 1
tD
DOUT 0
MCT03390
Figure 11-17 SSC Slave Mode Timing
Semiconductor Group
11-11
1997-10-01
Device Specifications C540U / C541U
11.4 AC Characteristics of Programming Mode
VCC = 5 V 10 %; VPP = 11.5 V 5 %; TA = 25 C 10 C
Parameter ALE pulse width PMSEL setup to ALE rising edge Symbol min. Limit Values max. - - - - - - - - - - 75 20 - 20 - ns ns ns ns ns ns s ns ns ns ns ns s ns 500 ns ns 35 10 10 10 100 0 10 10 100 100 - - 0 - 1 100 83.3 Unit
tPAW tPMS
Address setup to ALE, PROG, or PRD falling tPAS edge Address hold after ALE, PROG, or PRD falling edge Address, data setup to PROG or PRD Address, data hold after PROG or PRD PMSEL setup to PROG or PRD PMSEL hold after PROG or PRD PROG pulse width PRD pulse width Address to valid data out PRD to valid data out Data hold after PRD Data float after PRD
tPAH tPCS tPCH tPMS tPMH tPWW tPRW tPAD tPRD tPDH tPDF
PROG high between two consecutive PROG tPWH1 low pulses PRD high between two consecutive PRD low tPWH2 pulses XTAL clock period
tCLKP
Semiconductor Group
11-12
1997-10-01
Device Specifications C540U / C541U
t PAW
PALE
t PMS
PMSEL1,0 H, H
t PAS
Port 2 A8-A13
t PAH
A0-A7
Port 0
D0-D7
PROG
t PWH t PCS t PWW t PCH
MCT03369
Figure 11-18 Programming Code Byte - Write Cycle Timing
Semiconductor Group
11-13
1997-10-01
Device Specifications C540U / C541U
t PAW
PALE
t PMS
PMSEL1,0 H, H
t PAS
Port 2 A8-13
t PAH
A0-7
t PAD
Port 0 D0-7
t PDH
t PRD
PRD
t PDF t PWH
t PCS
Notes: PROG must be high during a programming read cycle.
t PRW
t PCH
MCT03392
Figure 11-19 Verify Code Byte - Read Cycle Timing
Semiconductor Group
11-14
1997-10-01
Device Specifications C540U / C541U
PMSEL1,0
H, L
H, L
Port 0
D0, D1
D0, D1
t PCS t PMS
PROG
t PCH t PMH t PDH t PWW t PMS t PRD t PRW t PMH t PDF
PRD Note: PALE should be low during a lock bit read / write cycle.
MCT03393
Figure 11-20 Lock Bit Access Timing
PMSEL1,0
L, H
Port 2
e. g. FD H
t PCH
Port 0 D0-7
t PCS t PRD t PMS
PRD
t PDH t PDF t PMH
t PRW
Note: PROG must be high during a programming read cycle.
MCT03394
Figure 11-21 Version Byte Read Timing
Semiconductor Group
11-15
1997-10-01
Device Specifications C540U / C541U
11.5 OTP Verification Characteristics OTP Verification Mode for Protection Level 1 Parameter ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency Symbol min. Limit Values typ 2 tCLCL 12 tCLCL - - max. - - 4 tCLCL - - 6 ns ns ns ns ns MHz - - - 8 tCLCL - 4 Unit
tAWD tACY tDVA tDSA tAS
1/tCLCL
tCLCL
-
t ACY t AWD
ALE
t DSA t DVA
Port 0 Data Valid
t AS
P3.5
MCT02613
Figure 11-22 OTP Verification Mode for Protection Level 1
Semiconductor Group
11-16
1997-10-01
Device Specifications C540U / C541U
11.6 USB Transceiver Characteristics
VCC = 4.0V to 5.5V (5V +10%, -20%); VSS = 0 V
Parameter Output impedance (high state) Output impedance (low state) Input leakage current Tristate output off-state current Crossover point
Notes :
TA = 0 to 70 C
Limit Values min. max. 43 51 5 10 2.0 A A V
1)
Symbol
Unit
Test Condition
RDH RDL II I OZ VCR
28 28 - - 1.3
VIN = VSS or VCC VOUT = VSS or VCC 1)
2)
1) This value includes an external resistor of 30 1% (see "Load for D+/D-" diagram for testing details) 2) The crossover point is in the range of 1.3V to 2.0V for the high speed mode with a 50pF capacitance. In the low-speed mode with a 100pF or greater capacitance, the crossover point is in the range of 1.3V to 2.0V.
Parameter High speed mode rise time High speed mode fall time Low speed mode rise time Low speed mode fall time
Symbol min.
Limit Values max. 20 20 300 300 4 4 75 75
Unit ns ns ns ns
tFR tFF tLR tLF
Semiconductor Group
11-17
1997-10-01
Device Specifications C540U / C541U
VCC -0.5 V
0.2 VCC+0.9 Test Points 0.2 VCC -0.1
MCT00039
0.45 V
AC Inputs during testing are driven at VCC - 0.5 V for a logic '1' and 0.45 V for a logic '0'. Timing measurements are made at VIHmin for a logic '1' and VILmax for a logic '0'. Figure 11-23 AC Testing: Input, Output Waveforms
VLoad +0.1 V VLoad VLoad -0.1 V
Timing Reference Points
VOH -0.1 V
VOL +0.1 V
MCT00038
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH 20 mA Figure 11-24 AC Testing : Float Waveforms
2.8 V Test Point 1.5 k *)
30 k D.U.T 15 k
S1
CL
Test S1 Close Open Open Close
MCS03425
C L = 50 pF, full speed C L = 50 pF, low speed (min. timing) C L = 350 pF, low speed (max. timing) *) 1.5 k on D- (low speed) or D+ (full speed) only
D- / LS D+ / LS D- / FS D+ / FS
Figure 11-25 Load for D+/D-
Semiconductor Group
11-18
1997-10-01
Device Specifications C540U / C541U
Crystal Oscillator Mode C XTAL2 2 - 12 MHz XTAL1 C Crystal Mode: C = 20 pF 10 pF (Incl. Stray Capacitance)
Driving from External Source N.C. XTAL2
External Oscillator Signal
XTAL1
MCS03426
Figure 11-26 Recommended Oscillator Circuits for Crystal Oscillator
Semiconductor Group
11-19
1997-10-01
Device Specifications C540U / C541U
11.7 Package Information
Plastic Package, P-LCC-44-1 (SMD) (Plastic Leaded Chip Carrier Package)
Figure 11-27 P-LCC-44-1 Package Outline
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Semiconductor Group 11-20
Dimensions in mm 1997-10-01
GPL05102
Device Specifications C540U / C541U
Plastic Package, P-SDIP-52-1 (Plastic Shrink Dual In-Line Package)
Figure 11-28 P-SDIP-52-1 Package Outline
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" Dimensions in mm Semiconductor Group 11-21 1997-10-01
GPD05262
Device Specifications C540U / C541U
Semiconductor Group
11-22
1997-10-01
Index C540U / C541U
12
Index
Note : Bold page numbers refer to the main definition part of SFRs or SFR bits.
BRS0 . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-28 BRS1 . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-28 BRS2 . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-28
A
A06-A03 . . . . . . . . . . . . . . . . . . . . 3-8, 6-72 A16-A13 . . . . . . . . . . . . . . . . . . . . 3-8, 6-72 A26-A23 . . . . . . . . . . . . . . . . . . . . 3-9, 6-72 A36-A33 . . . . . . . . . . . . . . . . . . . . 3-9, 6-72 A46-A43 . . . . . . . . . . . . . . . . . . . . 3-9, 6-72 Absolute maximum ratings . . . . . . . . . . 11-1 AC . . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-7 AC characteristics . . . . . . . . . 11-4 to 11-19 Data memory read cycle. . . . . . . . . . 11-8 Data memory write cycle . . . . . . . . . 11-9 External clock timing. . . . . . . . . . . . . 11-9 Lock bit access timing. . . . . . . . . . . 11-15 Program memory read cycle. . . . . . . 11-7 Programming mode . . . . . . . . . . . . 11-12 Programming mode read cycle. . . . 11-14 Programming mode write cycle . . . 11-13 Protected ROM/OTP verify timing . 11-16 Version byte access timing . . . . . . . 11-15 AC Testing Float waveforms . . . . . . . . . . . . . . . 11-18 Input/output waveforms . . . . . . . . . 11-18 Load for D+/D- . . . . . . . . . . . . . . . . 11-18 ACC . . . . . . . . . . . . . . . . . . . . . 2-2, 3-4, 3-7 ACK0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 ACK1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 ACK2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 ACK3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 ACK4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 ACKn . . . . . . . . . . . . . . . . . . . . . 6-70, 7-12 ADROFF. . . . . . . . . . . . . . . . . 3-5, 3-7, 6-55 AIE0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 AIE1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 AIE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 AIE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 AIE4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 AIEn . . . . . . . . . . . . . . . . . . . . . . . 6-68, 7-7 ALE signal . . . . . . . . . . . . . . . . . . . . . . . 4-4 AO5-0 . . . . . . . . . . . . . . . . . . . . . . 3-7, 6-55
C
C/T . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-16 CBF0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 CBF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 CBF2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 CBF3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 CBF4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 CBFn . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66 CLREP0. . . . . . . . . . . . . . . . . . . . . . . . . 3-8 CLREP1. . . . . . . . . . . . . . . . . . . . . . . . . 3-8 CLREP2. . . . . . . . . . . . . . . . . . . . . . . . . 3-9 CLREP3. . . . . . . . . . . . . . . . . . . . . . . . . 3-9 CLREP4. . . . . . . . . . . . . . . . . . . . . . . . . 3-9 CLREPn. . . . . . . . . . . . . . . . . . . . . . . . 6-67 CPHA. . . . . . . . . . . . . . . . . . . . . . 3-6, 6-28 CPOL . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-28 CPU Accumulator . . . . . . . . . . . . . . . . . . . . 2-2 B register . . . . . . . . . . . . . . . . . . . . . . 2-3 Basic timing . . . . . . . . . . . . . . . . . . . . 2-4 Fetch/execute diagram. . . . . . . . . . . . 2-5 Functionality . . . . . . . . . . . . . . . . . . . . 2-2 Program status word . . . . . . . . . . . . . 2-2 Stack pointer . . . . . . . . . . . . . . . . . . . 2-3 CPU timing. . . . . . . . . . . . . . . . . . . . . . . 2-5 CY . . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-7
D
DA . . . . . . . . . . . . . . . . . . . . . . . . 3-8, 6-57 DADD. . . . . . . . . . . . . . . . . . . . . . 3-7, 6-76 DAI. . . . . . . . . . . . . . . . . . . . 3-8, 6-62, 7-11 DAIE . . . . . . . . . . . . . . . . . . . 3-8, 6-60, 7-6 DBM0. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 DBM1. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 DBM2. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 DBM3. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 DBM4. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 DBMn. . . . . . . . . . . . . . . . . . . . . . . . . . 6-65 DC characteristics . . . . . . . . . . 11-2 to 11-3 DCR . . . . . . . . . . . . . . . . . . . . 3-5, 3-8, 6-57 DDI. . . . . . . . . . . . . . . . . . . . 3-8, 6-62, 7-11 DDIE . . . . . . . . . . . . . . . . . . . 3-8, 6-60, 7-6 Device characteristics . . . . . . 11-1 to 11-21 DIER . . . . . . . . . . . . . . . 3-5, 3-8, 6-60, 7-6 DINIT . . . . . . . . . . . . . . . . . . . . . . 3-8, 6-58 1997-10-01
B
B . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-4, 3-7 Basic CPU timing . . . . . . . . . . . . . . . . . . 2-4 Block diagram. . . . . . . . . . . . . . . . . . . . . 2-1
Semiconductor Group
12-1
Index C540U / C541U
DIR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 DIR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 DIR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 DIR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 DIR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 DIRn . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66 DIRR. . . . . . . . . . . . . . . 3-5, 3-8, 6-62, 7-11 DNR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 DNR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 DNR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 DNR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 DNR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 DNRIE0 . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 DNRIE1 . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 DNRIE2 . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 DNRIE3 . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 DNRIE4 . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 DNRIEn . . . . . . . . . . . . . . . . . . . . 6-68, 7-7 DNRn . . . . . . . . . . . . . . . . . . . . . 6-70, 7-12 DONE0 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 DONE1 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 DONE2 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 DONE3 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 DONE4 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 DONEn . . . . . . . . . . . . . . . . . . . . . . . . . 6-67 DPH . . . . . . . . . . . . . . . . . . . . . . . . 3-4, 3-6 DPL . . . . . . . . . . . . . . . . . . . . . . . . 3-4, 3-6 DPWDR . . . . . . . . . . . . . . . . . 3-5, 3-8, 6-59
E
EA. . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-4 EALE . . . . . . . . . . . . . . . . . . . . . . . 3-7, 4-4 Emulation concept . . . . . . . . . . . . . . . . . 4-5 EOD0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 EOD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 EOD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 EOD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 EOD4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 EODIE0 . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 EODIE1 . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 EODIE2 . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 EODIE3 . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 EODIE4 . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 EODIEn . . . . . . . . . . . . . . . . . . . . 6-69, 7-7 EODn . . . . . . . . . . . . . . . . . . . . . 6-70, 7-12 EPBA0 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 EPBA1 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 EPBA2 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
EPBA3 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 EPBA4 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 EPBAn . . . . . . . . . . . . . . . . . . . . . 3-5, 6-72 EPBC0 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 EPBC1 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 EPBC2 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 EPBC3 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 EPBC4 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 EPBCn . . . . . . . . . . . . . . . . . . 3-5, 6-64, 7-8 EPBS0 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 EPBS1 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 EPBS2 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 EPBS3 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 EPBS4 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 EPBSn . . . . . . . . . . . . . . . . . . . . . 3-5, 6-66 EPI4-0 . . . . . . . . . . . . . . . . . 3-7, 6-56, 7-13 EPIE0. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 EPIE1. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 EPIE2. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 EPIE3. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 EPIE4. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 EPIEn. . . . . . . . . . . . . . . . . . . 3-5, 6-68, 7-7 EPIR0 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 EPIR1 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 EPIR2 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 EPIR3 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 EPIR4 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 EPIRn . . . . . . . . . . . . . . . . . 3-5, 6-70, 7-12 EPLEN0 . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 EPLEN1 . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 EPLEN2 . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 EPLEN3 . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 EPLEN4 . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 EPLENn . . . . . . . . . . . . . . . . . . . . 3-5, 6-72 EPS2-0 . . . . . . . . . . . . . . . . . . . . 3-7, 6-53 EPS7 . . . . . . . . . . . . . . . . . . . . . . 3-7, 6-53 EPSEL . . . . . . . . . . . . . . . . . . 3-5, 3-7, 6-53 ESP0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 ESP1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 ESP2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 ESP3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 ESP4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 ESPn . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66 ESSC . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-5 ET0 . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-4 ET1 . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-4 EUDI . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-5
Semiconductor Group
12-2
1997-10-01
Index C540U / C541U
EUEI . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-5 EWPD. . . . . . . . . . . . . . . . . . . . . . . 3-6, 9-2 EX0. . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-4 EX1. . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-4 Execution of instructions . . . . . . . . 2-4, 2-5 External bus interface. . . . . . . . . . 4-1 to 4-4 ALE signal. . . . . . . . . . . . . . . . . . . . . . 4-4 ALE switch-off control . . . . . . . . . . . . . 4-4 Overlapping of data/program memory 4-3 Program memory access . . . . . . . . . . 4-3 Program/data memory timing . . . . . . . 4-2 PSEN signal . . . . . . . . . . . . . . . . . . . . 4-3 Role of P0 and P2. . . . . . . . . . . . . . . . 4-1
F
F0 . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-7 F1 . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-7 Fail save mechanisms . . . . . . . . . 8-1 to 8-7 Fast power-on reset . . . . . . . . . . . . 5-3, 8-7 Features . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 FNR10-0. . . . . . . . . . . . . . . . . . . . 3-8, 6-63 FNRH . . . . . . . . . . . . . . . . . . . 3-5, 3-8, 6-63 FNRL . . . . . . . . . . . . . . . . . . . 3-5, 3-8, 6-63 Functional units . . . . . . . . . . . . . . . . . . . 1-1 Fundamental structure . . . . . . . . . . . . . . 2-1
IE1 . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-9 IEN0. . . . . . . . . . . . . . . . . . . . . 3-4, 3-6, 7-4 IEN1. . . . . . . . . . . . . . . . . . . . . 3-4, 3-6, 7-5 INCE0 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 INCE1 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 INCE2 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 INCE3 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 INCE4 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 INCEn . . . . . . . . . . . . . . . . . . . . . . . . . 6-65 INT0 . . . . . . . . . . . . . . . . . . . . . . . 3-7, 7-18 INT1 . . . . . . . . . . . . . . . . . . . . . . . 3-7, 7-18 Interrupts . . . . . . . . . . . . . . . . . . 7-1 to 7-20 Entry sequence timing . . . . . . . . . . . 7-16 External interrupts . . . . . . . . . . . . . . 7-18 Handling procedure . . . . . . . . . . . . . 7-16 Registers . . . . . . . . . . . . . . . . 7-4 to 7-14 Request flags . . . . . . . . . . . . . . . . . . . 7-9 Response time . . . . . . . . . . . . . . . . . 7-20 Sources and vector addresses. . . . . 7-17 IP0 . . . . . . . . . . . . . . . . . . . . . 3-4, 3-7, 7-14 IP1 . . . . . . . . . . . . . . . . . . . . . . . . 3-4, 7-14 IT0 . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-9 IT1 . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-9 ITCON . . . . . . . . . . . . . . . . . . 3-4, 3-6, 7-19
G
GATE . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-16 GEPIE0 . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 GEPIE1 . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 GEPIE2 . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 GEPIE3 . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 GEPIE4 . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 GEPIEn . . . . . . . . . . . . . . . . . . . . 6-64, 7-8 GEPIR . . . . . . . . . . . . . 3-5, 3-7, 6-56, 7-13 GF0 . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 9-2 GF1 . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 9-2
L
L06-L00 . . . . . . . . . . . . . . . . . . . . 3-8, 6-72 L16-L10 . . . . . . . . . . . . . . . . . . . . 3-8, 6-72 L26-L20 . . . . . . . . . . . . . . . . . . . . 3-9, 6-72 L36-L30 . . . . . . . . . . . . . . . . . . . . 3-9, 6-72 L46-L40 . . . . . . . . . . . . . . . . . . . . 3-9, 6-72 LED0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 LED1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 LED2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Logic symbol . . . . . . . . . . . . . . . . . . . . . 1-3 LOOPB . . . . . . . . . . . . . . . . . . . . 3-6, 6-31 LSBSM. . . . . . . . . . . . . . . . . . . . . 3-6, 6-31
H
Hardware reset. . . . . . . . . . . . . . . . . . . . 5-1
M
M0 . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-16 M1 . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-16 Memory organization . . . . . . . . . . . . . . . 3-1 Data memory . . . . . . . . . . . . . . . . . . . 3-2 General purpose registers . . . . . . . . . 3-2 Memory map . . . . . . . . . . . . . . . . . . . 3-1 Program memory . . . . . . . . . . . . . . . . 3-2 MSTR. . . . . . . . . . . . . . . . . . . . . . 3-6, 6-27
I
I/O ports . . . . . . . . . . . . . . . . . . . 6-1 to 6-12 I0ETF . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-19 I0ETR . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-19 I1ETF . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-19 I1ETR . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-19 IDLE . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 9-2 IDLS . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 9-2 IE0 . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-9
Semiconductor Group
12-3
1997-10-01
Index C540U / C541U
N
NACK0 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 NACK1 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 NACK2 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 NACK3 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 NACK4 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 NACKn . . . . . . . . . . . . . . . . . . . . 6-70, 7-12 NAIE0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 NAIE1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 NAIE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 NAIE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 NAIE4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 NAIEn . . . . . . . . . . . . . . . . . . . . . . 6-68, 7-7 NOD0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 NOD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 NOD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 NOD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 NOD4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 NODIE0 . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 NODIE1 . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 NODIE2 . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 NODIE3 . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 NODIE4 . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 NODIEn . . . . . . . . . . . . . . . . . . . . 6-68, 7-7 NODn . . . . . . . . . . . . . . . . . . . . . 6-70, 7-12
Programming mode . . . . . . . . . . . . . 10-1 Version byte access . . . . . . . . . . . . 10-12 OV . . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-7 OWDS . . . . . . . . . . . . . . . . . . . . . . 3-7, 8-3
P
P . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-7 P0 . . . . . . . . . . . . . . . . . . . . . . . . . 3-4, 3-6 P1 . . . . . . . . . . . . . . . . . . . . . . . . . 3-4, 3-6 P2 . . . . . . . . . . . . . . . . . . . . . . . . . 3-4, 3-6 P3 . . . . . . . . . . . . . . . . . . . . . . . . . 3-4, 3-7 Package information P-LCC-44 package. . . . . . . . . . . . . 11-20 P-SDIP-52 package . . . . . . . . . . . . 11-21 PAGE0. . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 PAGE1. . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 PAGE2. . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 PAGE3. . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 PAGE4. . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 PAGEn. . . . . . . . . . . . . . . . . . . . . . . . . 6-72 Parallel I/O . . . . . . . . . . . . . . . . . 6-1 to 6-12 PCLK . . . . . . . . . . . . . . . . . . . . . . 3-8, 6-58 PCON . . . . . . . . . . . . . . . . . . . 3-5, 3-6, 9-2 PCON1 . . . . . . . . . . . . . . . . . . 3-5, 3-6, 9-2 PDE . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 9-2 PDS . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 9-2 Pin configuration . . . . . . . . . . . . . 1-4 to 1-5 P-LCC-44 package. . . . . . . . . . . . . . . 1-4 P-SDIP-52 package . . . . . . . . . . . . . . 1-5 Pin definitions and functions . . . . 1-6 to 1-9 Ports . . . . . . . . . . . . . . . . . . . . . 6-1 to 6-12 Alternate functions . . . . . . . . . . 6-8 to 6-9 Port loading and interfacing . . . . . . . 6-11 Port timing . . . . . . . . . . . . . . . . . . . . 6-10 Quasi-bidirectional port structure Output driver circuitry . . . . . . . . . . . 6-4 Port 0/2 as address/data bus . . . . . 6-7 Read-modify-write function . . . . . . . 6-12 Power saving modes . . . . . . . . . . 9-1 to 9-8 Behaviour of external pins . . . . . . . . . 9-3 Idle mode . . . . . . . . . . . . . . . . . 9-3 to 9-4 Power down mode . . . . . . . . . . 9-5 to 9-8 Entering . . . . . . . . . . . . . . . . . . . . . 9-6 External wake-up timing . . . . . . . . . 9-7 Functionality . . . . . . . . . . . . . . . . . . 9-5 Termination. . . . . . . . . . . . . . . . . . . 9-7 Power supply current . . . . . . . . . . . . . . 11-3 PSEN signal. . . . . . . . . . . . . . . . . . . . . . 4-3
O
Oscillator operation . . . . . . . . . . . 5-6 to 5-8 External clock source . . . . . . . . . . . . . 5-8 On-chip oscillator circuitry. . . . . . . . . . 5-8 Recommended oscillator circuit . . . . . 5-7 Oscillator watchdog . . . . . . . . . . . 8-5 to 8-7 Behaviour at reset. . . . . . . . . . . . . . . . 5-3 Block diagram . . . . . . . . . . . . . . . . . . . 8-6 OTP memory operation . . . . . 10-1 to 10-14 Access mode selection . . . . . . . . . . . 10-7 Basic prog. mode selection. . . . . . . . 10-6 Lock bit access . . . . . . . . . . . . . . . . 10-10 OTP memory protection levels . . . . 10-10 OTP protection Level 1 verifiy timimg. . . . . . . . . . 10-13 OTP verification example . . . . . . 10-14 Protection level 1. . . . . . . . . . . . . 10-13 Pin configuration P-LCC-44 package . . . . . . . . . . . . 10-2 P-SDIP-52 package . . . . . . . . . . . 10-3 Pin definitions and functions . . 10-4, 10-5 Program/read operation . . . . . 10-8, 10-9 Semiconductor Group 12-4
1997-10-01
Index C540U / C541U
PSSC . . . . . . . . . . . . . . . . . . . . . . 3-7, 7-14 PSW . . . . . . . . . . . . . . . . . . . . . 2-3, 3-4, 3-7 PT0. . . . . . . . . . . . . . . . . . . . . . . . 3-7, 7-14 PT1. . . . . . . . . . . . . . . . . . . . . . . . 3-7, 7-14 PUDI. . . . . . . . . . . . . . . . . . . . . . . 3-7, 7-14 PUEI . . . . . . . . . . . . . . . . . . . . . . . 3-7, 7-14 PX0. . . . . . . . . . . . . . . . . . . . . . . . 3-7, 7-14 PX1. . . . . . . . . . . . . . . . . . . . . . . . 3-7, 7-14
R
RD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Recommended oscillator circuits . . . . 11-19 Reset . . . . . . . . . . . . . . . . . . . . . . 5-1 to 5-5 Fast power-on reset . . . . . . . . . . . . . . 5-3 Hardware reset timing. . . . . . . . . . . . . 5-5 of USB module . . . . . . . . . . . . . . . . . . 5-2 Power-on reset timing. . . . . . . . . . . . . 5-4 Reset circuitries . . . . . . . . . . . . . . . . . 5-2 RLE0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 RLE1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 RLE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 RLE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 RLE4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 RLEIE0 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 RLEIE1 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 RLEIE2 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 RLEIE3 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 RLEIE4 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 RLEIEn . . . . . . . . . . . . . . . . . . . . . 6-68, 7-7 RLEn . . . . . . . . . . . . . . . . . . . . . 6-70, 7-12 RMAP . . . . . . . . . . . . . . . . . . . . . . . 3-3, 3-7 RPWD . . . . . . . . . . . . . . . . . . . . . 3-8, 6-59 RS0 . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-7 RS1 . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-7 RSM . . . . . . . . . . . . . . . . . . . . . . . 3-8, 6-58
S
SBI . . . . . . . . . . . . . . . . . . . . 3-8, 6-62, 7-11 SBIE . . . . . . . . . . . . . . . . . . . . 3-8, 6-60, 7-6 SCEN . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-27 SCF . . . . . . . . . . . . . . . 3-4, 3-6, 6-30, 7-10 SCIEN . . . . . . . . . . . . . . 3-4, 3-7, 6-29, 7-5 SCLK . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-21 SE0I . . . . . . . . . . . . . . . . . . . 3-8, 6-62, 7-11 SE0IE . . . . . . . . . . . . . . . . . . . 3-8, 6-60, 7-6 SEI . . . . . . . . . . . . . . . . . . . . 3-8, 6-62, 7-11 SEIE . . . . . . . . . . . . . . . . . . . . 3-8, 6-60, 7-6 SETRD0 . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 SETRD1 . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Semiconductor Group 12-5
SETRD2. . . . . . . . . . . . . . . . . . . . . . . . . 3-9 SETRD3. . . . . . . . . . . . . . . . . . . . . . . . . 3-9 SETRD4. . . . . . . . . . . . . . . . . . . . . . . . . 3-9 SETRDn. . . . . . . . . . . . . . . . . . . . . . . . 6-66 SETWR0 . . . . . . . . . . . . . . . . . . . . . . . . 3-8 SETWR1 . . . . . . . . . . . . . . . . . . . . . . . . 3-8 SETWR2 . . . . . . . . . . . . . . . . . . . . . . . . 3-9 SETWR3 . . . . . . . . . . . . . . . . . . . . . . . . 3-9 SETWR4 . . . . . . . . . . . . . . . . . . . . . . . . 3-9 SETWRn . . . . . . . . . . . . . . . . . . . . . . . 6-67 SLS . . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-21 SOD0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 SOD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 SOD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 SOD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 SOD4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 SODIE0 . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 SODIE1 . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 SODIE2 . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 SODIE3 . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 SODIE4 . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 SODIEn . . . . . . . . . . . . . . . . . . . . 6-69, 7-7 SODn . . . . . . . . . . . . . . . . . . . . . 6-71, 7-12 SOFDE0 . . . . . . . . . . . . . . . . . . . . . . . . 3-8 SOFDE1 . . . . . . . . . . . . . . . . . . . . . . . . 3-8 SOFDE2 . . . . . . . . . . . . . . . . . . . . . . . . 3-9 SOFDE3 . . . . . . . . . . . . . . . . . . . . . . . . 3-9 SOFDE4 . . . . . . . . . . . . . . . . . . . . . . . . 3-9 SOFDEn . . . . . . . . . . . . . . . . . . . . . . . 6-64 SOFI . . . . . . . . . . . . . . . . . . 3-8, 6-62, 7-11 SOFIE . . . . . . . . . . . . . . . . . . 3-8, 6-61, 7-6 SP . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-4, 3-6 Special Function Registers . . . . . . . . . . 3-3 Access with RMAP. . . . . . . . . . . . . . . 3-3 Table - address ordered. . . . . . 3-6 to 3-9 Table - functional order . . . . . . 3-4 to 3-5 SPEED. . . . . . . . . . . . . . . . . . . . . 3-8, 6-57 SRB . . . . . . . . . . . . . . . . . . . . 3-4, 3-6, 6-31 SRI. . . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-21 SSC interface. . . . . . . . . . . . . . 6-21 to 6-31 Baudrate generation. . . . . . . . . . . . . 6-23 Block diagram . . . . . . . . . . . . . . . . . 6-21 General operation . . . . . . . . . . . . . . 6-22 Master mode timing . . . . . . . . . . . . . 6-25 Master/slave mode. . . . . . . . . . . . . . 6-24 Registers . . . . . . . . . . . . . . . 6-27 to 6-31 Slave mode timing . . . . . . . . . . . . . . 6-26
1997-10-01
Index C540U / C541U
Write collision detection . . . . . . . . . . 6-23 SSCCON . . . . . . . . . . . . . . . . 3-4, 3-6, 6-27 SSCMOD . . . . . . . . . . . . . . . . 3-4, 3-6, 6-31 STALL0 . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 STALL1 . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 STALL2 . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 STALL3 . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 STALL4 . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 STALLn . . . . . . . . . . . . . . . . . . . . . . . . 6-64 STB . . . . . . . . . . . . . . . . . . . . 3-4, 3-6, 6-31 STI . . . . . . . . . . . . . . . . . . . . 3-8, 6-62, 7-11 STIE . . . . . . . . . . . . . . . . . . . . 3-8, 6-60, 7-6 STO . . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-21 SUI . . . . . . . . . . . . . . . . . . . . 3-8, 6-62, 7-11 SUIE . . . . . . . . . . . . . . . . . . . . 3-8, 6-61, 7-6 SUSP . . . . . . . . . . . . . . . . . . . . . . 3-8, 6-57 SWDT. . . . . . . . . . . . . . . . . . . . . . . 3-7, 8-3 SWR . . . . . . . . . . . . . . . . . . . . . . . 3-8, 6-57 SYSCON . . . . . . . . . . . . . 3-3, 3-4, 3-7, 4-4
SSC timing . . . . . . . . . . . . . . . . . . . 11-10 Version byte access timing . . . . . . 11-15 TL0. . . . . . . . . . . . . . . . . . . . . 3-4, 3-6, 6-14 TL1. . . . . . . . . . . . . . . . . . . . . 3-4, 3-6, 6-14 TMOD . . . . . . . . . . . . . . . . . . 3-4, 3-6, 6-16 TPWD . . . . . . . . . . . . . . . . . . . . . 3-8, 6-59 TR0 . . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-15 TR1 . . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-15 TRIO . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-31
U
UBF0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 UBF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 UBF2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 UBF3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 UBF4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 UBFn . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66 UCLK . . . . . . . . . . . . . . . . . . . . . . 3-8, 6-58 USB module. . . . . . . . . . . . . . . 6-32 to 6-75 Block diagram . . . . . . . . . . . . . . . . . 6-32 Control transfer . . . . . . . . . . . . . . . . 6-51 Detach/attach detection . . . . . . . . . . 6-76 Detection of connected devices . . . . 6-75 Device registers . . . . . . . . . . 6-57 to 6-63 Endpoint registers . . . . . . . . 6-64 to 6-72 Global registers . . . . . . . . . . 6-53 to 6-56 Initialization . . . . . . . . . . . . . . . . . . . 6-49 Memory buffer address generation . 6-48 Memory buffer modes . . . . . 6-34 to 6-46 Double buffer mode . . . . . 6-40 to 6-46 Single buffer mode . . . . . . 6-35 to 6-39 Memory buffer organization . . . . . . . 6-47 On-chip USB transceiver . . . . . . . . . 6-73 Register set . . . . . . . . . . . . . 6-52 to 6-72 Transfer modes . . . . . . . . . . . . . . . . 6-33 USBVAL. . . . . . . . . . . . . . . . . 3-5, 3-7, 6-54
T
T0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 T1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 TC. . . . . . . . . . . . . . . . . . . . . 3-6, 6-30, 7-10 TCEN . . . . . . . . . . . . . . . . . . . 3-7, 6-29, 7-5 TCON . . . . . . . . . . . . . . . 3-4, 3-6, 6-15, 7-9 TEN . . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-27 TF0 . . . . . . . . . . . . . . . . . . . . . 3-6, 6-15, 7-9 TF1 . . . . . . . . . . . . . . . . . . . . . 3-6, 6-15, 7-9 TH0. . . . . . . . . . . . . . . . . . . . . 3-4, 3-6, 6-14 TH1. . . . . . . . . . . . . . . . . . . . . 3-4, 3-6, 6-14 Timer/counter . . . . . . . . . . . . . . . . . . . . 6-13 Timer/counter 0 and 1. . . . . . 6-13 to 6-20 Mode 0, 13-bit timer/counter . . . . . 6-17 Mode 1, 16-bit timer/counter . . . . . 6-18 Mode 2, 8-bit rel. timer/counter . . . 6-19 Mode 3, two 8-bit timer/counter. . . 6-20 Registers . . . . . . . . . . . . . . 6-14 to 6-16 Timings Data memory read cycle. . . . . . . . . . 11-8 Data memory write cycle . . . . . . . . . 11-9 External clock timing. . . . . . . . . . . . . 11-9 Lock bit access timing. . . . . . . . . . . 11-15 Program memory read cycle. . . . . . . 11-7 Programming mode read cycle. . . . 11-14 Programming mode write cycle . . . 11-13 Protected ROM/OTP verify timing . 11-16 ROM verification mode 2 . . . . . . . . 11-16
V
Version bytes . . . . . . . . . . . . . . . . . . . 10-12 Version registers . . . . . . . . . . . . . . . . 10-12 VR0 . . . . . . . . . . . . . . . . . . . 3-4, 3-7, 10-12 VR1 . . . . . . . . . . . . . . . . . . . 3-4, 3-7, 10-12 VR2 . . . . . . . . . . . . . . . . . . . 3-4, 3-7, 10-12
W
Watchdog timer . . . . . . . . . . . . . . 8-1 to 8-4 Block diagram . . . . . . . . . . . . . . . . . . 8-1 Control/status flags . . . . . . . . . . . . . . 8-3 Input clock selection. . . . . . . . . . . . . . 8-2
Semiconductor Group
12-6
1997-10-01
Index C540U / C541U
Refreshing of the WDT . . . . . . . . . . . . 8-4 Reset operation . . . . . . . . . . . . . . . . . 8-4 Starting of the WDT . . . . . . . . . . . . . . 8-4 Time-out periods. . . . . . . . . . . . . . . . . 8-2 WCEN . . . . . . . . . . . . . . . . . . 3-7, 6-29, 7-5 WCOL. . . . . . . . . . . . . . . . . . 3-6, 6-30, 7-10 WDCON . . . . . . . . . . . . . . . . . . 3-4, 3-7, 8-3 WDT . . . . . . . . . . . . . . . . . . . . . . . . 3-7, 8-3 WDTPSEL . . . . . . . . . . . . . . . . . . . 3-6, 8-2 WDTREL . . . . . . . . . . . . . . . . . 3-4, 3-6, 8-2 WDTS. . . . . . . . . . . . . . . . . . . . . . . 3-7, 8-3 WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 WS . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 9-2
Semiconductor Group
12-7
1997-10-01

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